High speed programmable macrocell with combined path for storage and combinatorial modes

A macrocell for use in a programmable device, comprising:

• polarity multiplexer means responsive to a polarity multiplex signal for changing a polarity of output data of said macrocell from between active high and active low;
• a storage circuit coupled to said polarity multiplexer means for transmitting input data in accordance with a clock signal in a storage mode of operation;
• a combinatorial circuit coupled to aid polarity multiplexer means for transmitting said input data in a combinatorial mode of operation;
• wherein said storage circuit and said combinatorial circuit share one or more components selected from the group consisting of a slave circuit and a tri-state inverting buffer.

A macrocell for use in a programmable device, comprising:

• a master circuit having an input coupled to input data for passing data when in a combinatorial mode, and for selectively passing data when in a storage mode;
• a slave circuit including transmission means coupled to said master circuit for selectively blocking an output of said master circuit according to a first state of a clock signal when said macrocell is in said storage mode, and for passing said master circuit output when in said combinatorial mode;
• said slave circuit further including means responsive to an output of said transmission means for generating output data having true and complemented states in said storage and combinatorial modes, and for storing data during said first state of said clock signal when in said storage mode;
• and,
• a polarity multiplexer coupled to one of said master circuit and said slave circuit for varying an output polarity between active high and active low according to an output polarity signal.

A macrocell for use in a programmable device, comprising:

• a master circuit having an input coupled to input data for passing data when said macrocell is in a combinatorial mode, and for selectively passing data when in a storage mode;
• a slave circuit including transmission means coupled to said master circuit for selectively blocking an output of said master circuit according to a first state of a clock signal when said macrocell is in said storage mode, and for passing said master circuit output when in said combinatorial mode;
• said slave circuit further including means responsive to an output of said transmission means for generating output data having true and complemented states and for storing data during said first state of said clock signal, when in said storage mode, said generating and storing means of said slave circuit generating said true state of said output data when in said combinatorial mode;
• a polarity multiplexer coupled to one of said master circuit and said slave circuit for varying an output polarity between active high and active low according to an output polarity signal;
• and,
• bypass means coupled to said polarity multiplexer for generating said complemented state of said output data when in said combinatorial mode.

A macrocell for use in a programmable device, comprising:

• a master circuit including a first polarity multiplexer responsive to input data for generating a first signal in a storage mode of operation, said first signal corresponding to one of a true and complemented state of said input signal in accordance with a polarity configuration signal wherein said storage mode includes a latch mode and a registered mode;
• said master circuit further including means for storing said first signal in response to a transition from a first state to a second state of a clock signal when said macrocell is in said registered mode;
• a slave circuit including transmission means for selectively blocking an output of said master circuit during said first state and passing said master circuit output during said second state, when said macrocell is in said storage mode;
• said slave circuit further including means responsive to an output of said transmission means for generating output data having true and complemented states of said output data and for storing said output data during said first state of said clock signal, when said macrocell is in said storage mode;
• and,
• a second polarity multiplexer responsive to said input data for generating a second signal in a combinatorial mode of operation, said second signal corresponding to one of a true and complemented state of said input signal in accordance with said polarity configuration signal and defining said complemented state of said output data;
• said slave circuit being further operative for generating said true state of said output data when in said combinatorial mode.

A macrocell for use in a programmable device, comprising:

• polarity multiplex means responsive to a polarity multiplex signal for changing a polarity of output data of said macrocell between active high and active low;
• a storage circuit coupled to said polarity multiplex means for transmitting input data in accordance with a clock signal when said macrocell is in a storage mode of operation, said storage circuit thereby defining a storage signal path;
• a combinatorial circuit coupled to said polarity multiplex means for transmitting said input data when said macrocell is in a combinatorial mode of operation, said combinatorial circuit thereby defining a combinatorial signal path, said storage signal path and said combinatorial signal path having at least one common node;
• and,
• means coupled to said storage and combinatorial circuits for setting and resetting said output data according to set and reset signals, said setting and resetting means including a pullup transistor and a pulldown transistor respectively connected to said common node wherein said setting and resetting means are out of both said storage and combinatorial signal paths.