US 5,635,854 A · Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid

Abstract

A programmable logic device (PLD) integrated circuit containing an array of fuse or anti-fuse links includes verification circuitry configured to classify link resistances after programing into three resistance zones, corresponding to a "closed" state zone, an "open" state zone and a "forbidden" state zone intermediate the "closed" and "open" state zones. Two reference resistance values, namely a lower reference resistance value and the higher reference resistance value, divide the entire range of possible link resistance values into the aforementioned three resistance zones. Because the ratio between the higher reference resistance value and the lower reference resistance value is typically more than 50, the verification circuitry includes a switchable two level current source that produces a voltage across the link of correct dynamic range. A measurement voltage produced in response to the link voltage is compared by a pair of differential comparators to respective lower and higher reference voltages, the lower reference voltage corresponding to the measurement voltage that would be produced by a higher link voltage that is the product of the higher reference resistance value and the lower current level, and the higher reference voltage corresponding to the measurement voltage that would be produced by a lower link voltage that is the product of the lower reference resistance value and the higher current level.

Claims10

Dependent claims

A programmable logic device comprising:

a memory array of elements, each element having an electrical property, describable by a parameter, which is alterable from an initial condition in response to an application of energy directed to the element;
means for programming the memory array by applying energy directed to one or more elements of the array to attempt to produce a desired pattern in the array of said one or more elements having the values of their respective parameters lying in a first range of values and the other elements having the values of their respective parameters lying in a second range, there being a forbidden range of values of the parameter which is intermediate to the first and second ranges;
and
verification means for including a selected one of the elements in an electrical circuit and for in response to an electrical quantity in said circuit forming one or more digital signals from which it is determinable whether or not the value of the parameter of said element lies in the forbidden range;
wherein said elements are links, said parameter is one of link resistance and conductance, and said first range comprises values less than a lower reference value, said second range comprises values greater than a higher reference value, and said forbidden range comprises values between said lower and higher reference values, a ratio of said higher reference value to said lower reference value being at least 50 to 1.

2 more elements

Dependencies are inferred from the claim text.

Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid

Life of this patent

Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid

Life of this patent

Abstract

Claims10