Read and writable data bus particularly for programmable logic devices

A programmable logic device on an integrated circuit, comprising:

• a plurality of programmable logic cells having data output terminals and enable output terminals;
• a data bus including a plurality of sets of selectors arranged in a ring to provide a data bus readable and writable by the plurality of programmable logic cells, each selector in the plurality of sets of selectors having an output terminal, a control terminal, a ring input terminal, and a data input terminal, the ring input terminal connected to receive data from another selector in the ring, the data input terminal connected to the data output terminal of one programmable logic cells, the respective output terminal connected to supply data to the ring input terminals of a next selector in the ring, and the control terminal connected to the enable output terminal of one programmable logic cell, wherein signal on the control terminal determines whether the selector propagates a signal on the ring input terminal, or a data signal on the data input terminal;
• and
• a plurality of programmable segmentation circuits between adjacent pairs of sets of selectors in the plurality of sets, the programmable segmentation circuits having
• respective segmented states in which the output terminal of a last selector in a first set in said pair is connected to the ring input terminal of a first selector in the first set, and the output terminal of a last selector in a second set in said pair is connected to the ring input terminal of a first selector in the second set, and
• respective unsegmented states in which the output terminal of a last selector in the first set in said pair is connected to the ring input terminal of a first selector in the second set in said pair, and the output terminal of a last selector in the second set in said pair is connected to the ring input terminal of the first selector in the first set.