Zero power latchup suppression circuit

A zero power circuit comprising:

• power supply voltage pad;
• a battery pad;
• a power control circuit connected to the power supply voltage pad and the battery pad, wherein the power control circuit provides power to to a load by switching between the battery pad and the power supply voltage pad;
• and
• a suppression circuit connected in series between the power control circuit and the battery pad, the suppression circuit including:
• a resistor connected in series between the battery pad and the power control circuit, wherein current flowing through the resistor during a latchup condition causes a voltage to drop across the resistor, suppressing the latchup condition to the battery pad;
• and
• a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is shorted out when the transistor is turned on.

A latchup suppression circuit for use between a battery pad and a power control circuit comprising:

• a resistor connected in series between the battery pad and the power control circuit, wherein current flowing through the resistor during a latchup condition causes the voltage to drop across the resistor, suppressing the latchup condition to the battery pad;
• a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is shorted out when the transistor is turned on;
• an inverter circuit having an input and an output, wherein the input is connected to the power control circuit and the output is connected to the gate of the transistor;
• and
• a capacitive circuit having a first end connected between the output of the inverter circuit and the gate of the transistor and a second end connected to a power supply voltage, wherein the capacitive circuit provides a delay time before the transistor is turned on.

A zero power static random access memory device comprising:

• a power supply voltage;
• a battery power supply;
• a static random access memory;
• a power control circuit, wherein the power control circuit is connected to the power supply voltage, the battery power supply, and the static random access memory and provides power to the static random access memory by switching between the battery power supply and the power supply voltage pad;
• and
• a suppression circuit connected in series between the power control circuit and the battery power supply, the suppression circuit including:
• a resistor connected in series between the battery power supply and the power control circuit, wherein current flowing through the resistor during a latchup condition causes a voltage to drop across the resistor, suppressing the latchup condition to the battery power supply;
• and
• a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is substantially shorted when the transistor is turned on.

A method for preventing loss of power to a zero power circuit during surface mounting of the zero power circuit and for providing for latchup conditions, the method comprising:

• providing a resistor in series between a battery pad and a power control circuit;
• connecting a transistor in parallel with the resistor;
• and
• turning on the transistor when power to the zero power circuit is switched between a primary power source and a battery power source, wherein loss of power to the zero power circuit is prevented.

A zero power circuit comprising:

• a first power supply voltage input for connection to a first power supply;
• a second power supply voltage input for connection to a second power supply;
• a power control circuit coupled to the first power supply voltage input, the second power supply voltage input and a load, the power control circuit providing power to the load by switching between the first power supply voltage input and the second power supply voltage input;
• and
• a suppression circuit connected in series between the power control circuit and the second power supply voltage input, the suppression circuit including;
• a resistor connected in series between the second power supply and voltage input and the power control circuit, wherein current flowing through the resistor during a latchup condition causes a voltage to drop across the resistor, suppressing the latchup condition to the second power supply voltage input;
• and
• a switch connected in parallel with the resistor, wherein the switch may turned on and off so that the resistor is substantially shorted when the switch is turned on.

A system having a zero power circuit comprising:

• a primary power source;
• a secondary power source;
• a primary input coupled to the primary power source;
• a secondary input coupled to the secondary power source;
• a power control circuit, wherein the power control circuit is connected to the primary input, the secondary input, and a load and wherein the power control circuit provides power to the load by switching between the primary input and the secondary input;
• and
• a suppression circuit connected in series between the power control circuit and the secondary input, the suppression circuit including:
• a resistor connected in series between the secondary input and the power control circuit, wherein the current flowing through the resistor during a latchup condition causes a voltage to drop across the resistor, suppressing the latchup condition to the secondary input;
• and
• a switch connected in parallel with the resistor, wherein the switch may be turned on and off and wherein the resistor is substantially shorted when the switch is turned on.

A zero power static random access memory device comprising:

• a power supply voltage;
• a battery power supply;
• a static random access memory;
• a power control circuit, wherein the power control circuit is connected to the power supply voltage, the power supply, and the static random access memory and provides power to the static random access memory by switching between the battery power supply and the power supply voltage;
• and
• a suppression circuit connected in series between the power supply circuit and the battery power supply, the suppression circuit including:
• a resistor connected in series between the battery power supply and the power control circuit, wherein the current flowing through the resistor during a latchup condition causes a voltage to drop across the resistor, suppressing the latch-up condition to battery power supply;
• and
• a transistor connected in parallel with the resistor, wherein the transistor is turned on in response to a drop in the power supply voltage, wherein the resistor is substantially shorted when the transistor is turned on.