US 5,635,745 AGranted

Analog multiplexer cell for mixed digital and analog signal inputs

AssigneeNational Semiconductor Corporation

InventorWolfgang K. Hoeld

Life of this patent

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Abstract

An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor. The second N-channel transistor is on while the other three transistors are off and exhibits a drain/source on-resistance such that the lateral and vertical bipolar parasitic transistors formed by the second P-channel transistor will not turn on and there is no leakage current between the input of the cell and the output of the cell.

Claims10

Dependent claims

An input circuit for an integrated circuit formed in a substrate, the input circuit being for receiving either analog or digital input signals, comprising:

a circuit input terminal;
circuitry receiving a digital input signal and connected to said circuit input terminal;
a pass gate having an input terminal connected to said circuit input terminal and including a first field effect transistor of a first conductivity type and a second field effect transistor of said first conductive type connected in series to said first field effect transistor, said pass gate having an output terminal;
wherein said first and second field effect transistors are respectively formed in first and second doped well regions in said substrate, said first and second doped well regions being spaced apart;
wherein an input terminal of said first field effect transistor is connected to said circuit input terminal, and an output terminal of said first field effect transistor is connected to an input terminal of said second field effect transistor, and further comprising:
a third field effect transistor of a second conductivity type and having an input terminal connected to said output terminal of said first field effect transistor and an output terminal connected to a voltage reference;
and
a fourth field effect transistor of said second conductivity type and having an input terminal connected to said circuit input terminal and an output terminal connected to said pass gate output terminal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/302,308Filed 8 Sep 1994
Granted: 3 Jun 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 17/161
Modifications for eliminating interference voltages or currents: in field-effect transistor switches
H03K 17/162
In field-effect transistor switches: without feedback from the output circuit to the control circuit
H03K 17/6872
The output circuit comprising more than one controlled field-effect transistor: using complementary field-effect transistors
H03K 17/693
The devices being field-effect transistors: switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors