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US 5,635,731 AGranted
SRAM cell with no PN junction between driver and load transistors and method of manufacturing the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMotoi Ashida
Life of this patent
Estimating the term…
Abstract
SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.
Claims10
An SRAM cell comprising:
- a balk part including access transistors and driver transistors;
- and
- a load part including at least one thin film load transistor, said access transistors, driver transistors and load transistor being N-channel transistors.
An SRAM cell comprising:
- a balk part including access transistors and driver transistors;
- and
- a load part including at least one thin film load transistor, said access transistors, driver transistors and load transistor are P-channel transistors.
Dependencies are inferred from the claim text.