Method and apparatus for manufacturing known good semiconductor die
AssigneeMicron Technology, Inc.
InventorsWarren Farnworth, Alan Wood
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsWarren Farnworth, Alan Wood
Estimating the term…
A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
A method for manufacturing a semiconductor die comprising:
A method for fabricating a semiconductor die comprising:
A method for fabricating a known good semiconductor die comprising:
A method for manufacturing semiconductor dice comprising:
The method as claimed in 23 and wherein aligning the contact member is with optical alignment.
The method as claimed in claim 25 and wherein an assembly apparatus aligns the contact member and attaches the force distribution mechanism to the carrier.
Dependencies are inferred from the claim text.