Microprocessor using feedback memory address to internally generate bust mode transfer period signal for controlling burst mode data transfer to external memory

A data processing system comprising:

• a microprocessor supplying a memory address signal including an address of stored data and a designation signal for designating a period of burst mode transfer, said microprocessor including cache storage;
• a decoder for receiving and decoding said memory address signal and for outputting a decoded address signal;
• a memory control circuit for receiving said decoded address signal and for outputting memory control signals;
• a memory including a high speed storage region operating at a high speed to supply high speed data and a lower speed storage region operating at a lower speed than said high speed to supply lower speed data,
• said memory responding to said memory address signal and said memory control signals for outputting said high speed data and said lower speed data;
• and
• synchronous burst mode transfer means, responding independently of said memory control circuit to said designation signal for said period of burst mode transfer from said memory address signal supplied from said microprocessor, for transferring said high speed data and said lower speed data in a synchronous burst mode transfer from said memory to said cache storage.