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US 5,634,135 AGranted
Microprocessor with priority determination and priority based instruction selection
AssigneeTexas Instruments Incorporated
InventorJames F. Hollander
Life of this patent
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Abstract
A processor architecture comprises a priority processing unit (20), a priority memory (30), an instruction set memory (40), and an instruction execution unit (50). The priority processing unit (20) generates priority values and stores them in priority memory (30). Each priority value is associated with an instruction stored in instruction memory (40). Priority processing unit (20) causes the instruction associated with a particular priority value to be outputted to instruction execution unit (50).
Claims28
A processor, comprising:
- an instruction set memory operable to store a plurality of instructions representing an instruction set that are independent of order of execution;
- a priority memory coupled to said instruction memory and operable to store a plurality of priority values corresponding to respective ones of the instructions;
- an instruction execution unit coupled to said instruction set memory and operable to execute said instructions as a function of said priority values;
- a priority processing unit coupled to said priority memory and operable to generate said priority values and to output said priority values to said priority memory,
- wherein said priority processing unit comprises:
- a priority program memory operable to store a priority program operable to determine said priority values;
- and
- a processing unit coupled to said priority memory and operable to execute said priority program to determine said priority values.
5 more elements
A processor, comprising:
- an instruction set memory operable to store a plurality of instructions;
- a priority memory operable to store a plurality of priority values;
- an instruction execution unit coupled to said instruction memory operable to execute said instructions;
- a priority processing unit coupled to said priority memory operable to determine which of said instructions stored in said instruction memory are to be executed as a function of said priority values stored in said priority memory, said priority processing unit is further operable to generate said priority values corresponding to respective ones of said instructions and to output said priority values to said priority memory;
- and
- wherein said priority memory comprises a plurality of content-addressable memory locations, each of said memory locations associated with at least one of said instructions stored in said instruction set memory and responsive to a priority value from said priority processing unit to sense a match to initiate output of an instruction from said instruction set memory to said instruction execution unit.
3 more elements
A method of processing instructions, comprising the steps of:
- storing a plurality of instructions;
- storing a plurality of priority values associated with said plurality of instructions;
- storing a priority program to be used for determining said priority values;
- determining said priority values based on said priority program;
- determining which of said stored instructions is to be executed as a function of said priority values;
- and
- responsive to said step of determining, executing said instruction.
4 more elements
Dependencies are inferred from the claim text.