Computer processing unit employing a separate millicode branch history table

A computer processing system comprising:

• a memory mapped into at least a first and second region, said first region storing instructions belonging to a first instruction set architecture, and said second region storing instructions belonging to a second instruction set architecture of said computer unit, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction;
• an instruction buffer, coupled to said memory, for storing instructions that are executed by a processor unit;
• means for fetching instructions belonging to said first instruction set architecture from said first region of memory into said instruction buffer according to data stored in a first branch history table associated with instructions belonging to said first instruction set architecture in a first mode;
• and
• means for fetching instructions belonging to said second instruction set architecture from said second region of memory into said instruction buffer according to data stored in a second branch history table associated with instructions belonging to said second instruction set architecture in a second mode;
• wherein said second branch history table is separate from said first branch history table.

A computer processing unit comprising:

• a memory mapped into at least a first and second regions, said first region storing instructions belonging to a first instruction set architecture of said computer processing unit, and said second region storing instructions belonging to a second instruction set architecture of said computer processing system, wherein said first instruction set architecture includes at least one instruction that does not belong to said second instruction set architecture, wherein said at least one instruction belonging to said first instruction set architecture is implemented by a plurality of instructions belonging to said second instruction set architecture, and wherein said instructions belonging to said first instruction set architecture comprise at least one branch type instruction and said instructions belonging to said second instruction set architecture comprise at least one branch type instruction;
• an instruction buffer, coupled to said memory, for storing instructions that are executed by a processor unit;
• an instruction address register for storing an address of at least one instruction fetched from said memory into said instruction buffer;
• a first branch history table that, in a first mode, controls a multiplexer to load one of a target address and a next sequential address of an instruction belonging to said first instruction set architecture into said instruction address register in a second fetching cycle according to said address stored in said instruction address register in a first fetching cycle, wherein said second fetching cycle is subsequent to said first fetching cycle;
• and
• a second branch history table that, in a second mode, controls said multiplexer to load one of a target address and a next sequential address of an instruction belonging to said second instruction set architecture into said instruction address register in a fourth fetching cycle according to said address stored in said instruction address register in a third fetching cycle, wherein said fourth fetching cycle is subsequent to said third fetching cycle;
• wherein said second branch history table is separated from said first branch history table.