US 5,634,116 A · Non-integer multiple clock translator

Abstract

A multiple clock translator for a microprocessor is provided for synchronizing data from an external clock speed to an internal clock speed that is a non-integer multiple of the external clock speed. The translator comprises a latch circuit and a synchronization signal generator. The latch circuit receives data at the external clock speed and outputs data at the internal clock speed. The latch circuit includes an input latch and a sync latch, and receives an external clock having an enabling phase and an internal clock having an enabling phase. The input latch is docked by the enabling phase of the external clock, and the sync latch is docked by the enabling phase of the internal clock and enabled by a sync pulse. The synchronization signal generator generates a series of sync pulses that are output to the latch circuit in a selected pattern, wherein the pattern is a function of the non-integer multiple.

Claims12

Dependent claims

A method of synchronizing data from an external clock frequency of an external clock to an internal clock frequency of an internal clock of an apparatus that is a non-integer multiple of the external clock frequency, the method comprising the steps of:

generating a series of sync pulses in a selected pattern, wherein the pattern is a function of the non-integer multiple;
latching synchronous data in the apparatus that is received at the external frequency;
and
outputting the latched synchronous data from the apparatus in synchronization with the internal frequency, in response to the series of sync pulses.

1 more element

A multiple clock translator for synchronizing data from an external clock speed of an external clock to an internal clock speed of an internal clock of the multiple clock translator, wherein the internal clock speed is a non-integer multiple of the external clock speed, the translator comprising:

a latch circuit that receives data at the external clock speed and outputs data at the internal clock speed having an input latch and a sync latch, the latch circuit receiving an enabling phase of the external clock and an enabling phase of the internal clock, wherein the input latch is clocked by the enabling phase of the external clock, and the sync latch is clocked by the enabling phase of the internal clock and is enabled by a sync pulse;
and
a synchronization signal generator that generates a series of sync pulses that are output to the latch circuit in a selected pattern, wherein the pattern is a function of the non-integer multiple.

Dependencies are inferred from the claim text.

Non-integer multiple clock translator

Life of this patent

Non-integer multiple clock translator

Life of this patent

Abstract

Claims12