Cache coherency using flexible directory bit vectors
AssigneeSilicon Graphics, Inc.
InventorsJames P. Laudon, Daniel E. Lenoski
Life of this patent
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AssigneeSilicon Graphics, Inc.
InventorsJames P. Laudon, Daniel E. Lenoski
Estimating the term…
A memory controller in a computer system is described. The memory controller maintains a directory comprising a plurality of entries. Each entry is associated with a memory block. The memory controller maintains an entry of the directory in a modified fine bit vector format when a memory block associated with the entry is cached in one or more nodes all of which are within a single partition of the computer system. The entry when maintained in the modified fine bit vector format comprises a partition field storing information identifying the single partition, and a modified fine bit vector field storing information identifying nodes in the single partition where the memory block is cached. The memory controller maintains the entry in a modified coarse bit vector format when the memory block is cached in multiple nodes distributed among P partitions of the computer system, where P is greater than one. The entry when maintained in the modified coarse bit vector format comprises Q partition fields each storing information identifying one of the P partitions, and Q modified coarse bit vector fields each storing information identifying nodes in one of the P partitions where the memory block is cached.
In a node comprising at least a portion of main memory having a plurality of memory blocks, said node being part of a computer system having a plurality of partitions each comprising a plurality of nodes, a method for denoting nodes in which said memory blocks are cached, said method comprising the steps of:
In a node comprising at least a portion of main memory having a plurality of memory blocks, said node being part of a computer system having a plurality of partitions each comprising a plurality of nodes, a method for denoting nodes in which said memory blocks are cached, said method comprising the steps of:
In a node comprising at least a portion of main memory having a plurality of memory blocks, said node being part of a computer system having a plurality of partitions each comprising a plurality of nodes, a method for denoting nodes in which said memory blocks are cached, said method comprising the steps of:
A computer system, comprising:
In a node comprising at least a portion of main memory having a plurality of memory blocks, said node being part of a computer system having a plurality of partitions each comprising a plurality of nodes, a memory controller comprising:
In a node comprising at least a portion of main memory having a plurality of memory blocks, said node being part of a computer system having a plurality of partitions each comprising a plurality of nodes, a memory controller comprising:
Dependencies are inferred from the claim text.