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US 5,634,106 AGranted
Power saving system and method for refreshing a computer memory by switching between interval refresh and self-refresh operations
AssigneeKabushiki Kaisha Toshiba
InventorsKatsumi Yaezawa, Seiji Hinata
Life of this patent
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Abstract
A micro-computer system using a DRAM can refresh the DRAM in a certain interval cycle to maintain the memory contents or refresh the DRAM memory even when the system is set into the standby mode and the clock generator has stopped providing clock timing signals to the memory refreshing circuit. Accordingly, the DRAM memory is refreshed by automatically changing from the interval refresh mode to the self refresh mode when the system operation changes from the normal operation to the standby operation, thus achieving low system power consumption.
Claims13
A computer system comprising:
- a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals;
- a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle;
- a clock generator for supplying clock timing signals to elements of the system, including the CPU, the clock generator stopping the supply of clock timing signals when the CPU provides the standby mode instruction signal;
- a memory control means for providing memory operation control signals including at least two kinds of memory refresh instruction signals, one of the kinds of memory refresh instruction signals being an interval refresh signal, to the memory device in accordance with the normal mode and standby mode operation instruction signals from the CPU, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal;
- an interval refreshing means for executing an interval refresh operation of the memory device periodically in accordance with the clock timing signals while the CPU is providing the normal operation mode instruction signal to the memory control means;
- and
- a self-refreshing means for executing a self refresh operation of the memory device when the CPU provides the standby mode instruction signal to the memory control means in order to enter a standby mode of system operation.
4 more elements
A computer system comprising:
- a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals;
- a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle;
- a clock generator for supplying clock timing signals to elements of the system including the CPU,
- a memory control means for providing memory operation control signals including at least two kinds of memory refresh instruction signals, one of the kinds of memory refresh instruction signals being an interval refresh instruction signal, to the memory device in accordance with the normal mode and standby mode operation instruction signals from the CPU, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal;
- and
- a memory refreshing means for refreshing the memory device in accordance with the refresh instruction signals from the memory control means, wherein the memory refresh means executes an interval refresh operation of the memory device while the CPU provides the normal operation mode instruction signal to the memory control means and the memory refresh means executes a self-refresh operation of the memory device when the CPU provides the standby mode instruction signal to the memory control means and the memory control means instructs the memory refresh means to change memory refresh operation;
- wherein the clock generator stops supplying the clock timing signals to system elements when the memory device enters the self-refresh operation.
4 more elements
A computer system comprising:
- a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals;
- a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle;
- a clock generator for supplying clock timing signals to elements of the system, including the CPU, the clock generator ceasing to supply the timing signals when the system enters a standby mode of operation;
- a memory control means for providing memory operation control signals including first and second memory refresh instruction signals, the first memory refresh instruction signal being an interval refresh signal, in response to the normal mode and standby mode operation instruction signals, respectively, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal;
- a standby mode detector for providing a refresh mode change instruction signal to the memory control means in response to the standby mode operation instruction signal,
- an interval refreshing means for executing an interval refresh operation of the memory device periodically in accordance with the first refresh instruction signal, and
- a self-refreshing means for executing a self refresh operation of the memory device in accordance with the second refresh instruction signal during the standby mode of system operation.
4 more elements
A micro-computer system comprising:
- a DRAM memory requiring refreshing at a certain cycle to maintain its memory contents;
- a CPU for providing system operation instruction signals including normal operation mode and standby operation mode instruction signals;
- a clock generator for supplying clock signals to components of the system, including the CPU;
- a memory control means for providing memory operation control signals including two kinds of memory refresh signals, one of the kinds of memory refresh instruction signal being an interval refresh signal, to the DRAM memory in accordance with the system operation instruction signals, the memory control means providing a single first interval refresh signal to the DRAM memory just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal to the DRAM memory just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal;
- a detecting means for detecting the standby operation mode signal from the CPU and sending a self refresh operation instruction signal to the memory control means;
- and
- a memory refresh means for refreshing the DRAM memory in accordance with the refresh control signal from the memory control means;
- wherein, the memory refresh means executes an interval refresh operation of the DRAM memory when the CPU provides the normal operation mode instruction signal,
- the memory refresh means executes a self-refresh operation of the DRAM memory when the CPU provides the standby operation mode instruction signal, and
- the CPU sends a stop signal to the clock generator when the DRAM memory enters self-refresh operation.
7 more elements
Dependencies are inferred from the claim text.