US 5,634,105 AGranted

Semiconductor memory device to interface control signals for a DRAM to a SRAM

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorKanji Mizuno

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Abstract

In a semiconductor memory device in which row and column address signals are serially supplied using a multiplexer or serial address signals are supplied without using a multiplex, a RAM interface is provided which easily makes it possible to replace a DRAM with a SRAM. A memory IC which is formed by a DRAM is changed to a SRAM, and a resulting SRAM memory IC is controlled using a logic IC 10 which is originally constructed for use with the original DRAM memory IC. Between the logic IC and the SRAM memory IC, a RAM interface is disposed. According to the present invention, it is possible to divide row-column address signals which are supplied in serial form into row address signals and column address signals and to modify a control signal which controls a dynamic RAM to control a static RAM.

Claims8

Dependent claims

A RAM interface for receiving a control signal which controls a DRAM from a DRAM control device and applying the control signal to control a SRAM, comprising:

an address signal dividing means for dividing a serial row-column address signal from said DRAM control device into a row address signal and a column address signal wherein said address signal dividing means includes address signal latching means, a number of said address signal latching means being a same as a number of address lines,
and wherein said address signal latching means receive said serial row-column address signal and a RAS signal which instructs to fetch a row address signal, latch and output said row address signal at timing of said RAS signal while simultaneously outputting said serial row-column address signal as it presently is;
and
a static RAM control signal generating means for receiving said control signal to generate a control signal which controls said SRAM, wherein said static RAM control signal generating means includes a delay circuit for controlling a timing of outputting said control signal.

1 more element

Dependencies are inferred from the claim text.