Cache memory apparatus for reading data corresponding to input address information

A cache memory apparatus for reading data at a high speed corresponding to an input address information, the cache memory apparatus coupled to a main memory for storing a plurality of data each corresponding to a plurality of address information, each address information including a first address information and a second address information, and the cache memory apparatus having a first data group which is a part of the plurality of data, the cache memory apparatus comprising:

• a first memory for storing a portion of said first address information corresponding to said first data group;
• a second memory for storing a portion of said second address information corresponding to said first data group and said first data group;
• a mis-hit circuit for outputting a first select information, said mis-hit circuit receiving said input address information, generating and storing a first updating information updated by the first select information, and selectively outputting either the first updating information or said first address information of the input address information as the first select information;
• a first comparing circuit for comparing said first select information with said first address information stored in said first memory, said first comparing circuit determining whether the first select information is in accord or not with the first address information stored in said first memory;
• a register for storing and outputting said first address information of said input address information and for storing second address information;
• an updating circuit for outputting a second select information, the circuit receiving said input address information, generating a second updating information updated by the first address information of said input address information stored in said register, the updating circuit selectively outputting either said first address information or said second updating information as said second select information in accordance with a comparing result of said first comparing circuit;
• and
• a decoding circuit for outputting an inhibiting signal inhibiting transfer of an address corresponding to said second updating information to said main memory in accordance with a data read from said main memory according to said second updating information.