US 5,634,068 AGranted

Packet switched cache coherent multiprocessor system

AssigneeSun Microsystems, Inc.

InventorsSatyanarayana Nishtala, Zahir Ebrahim, William C. Van Loo, Kevin Normoyle, Leslie Kohn, Louis F. Coffin, III

Life of this patent

Estimating the term…

Loading patent…

Abstract

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems include a port that transmits and receives data as data packets of a fixed size. At least two of the sub-systems are data processors, each having a respective cache memory and a respective set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. The system controller maintains a set of duplicate cache tags (Dtags) for each of the data processors. The data processors each include master cache logic for updating the master cache tags, while the system controller includes logic for updating the duplicate cache tags. Memory transaction request logic simultaneously looks up the second cache tag in each of the sets of duplicate cache tags corresponding to the memory transaction request. It then determines which one of the cache memories and main memory to couple to the requesting data processor based on the second cache states and the address tags stored in the corresponding second cache tags. Duplicate cache update logic simultaneously updates all of the corresponding second cache tags in accordance with predefined cache tag update criteria.

Claims11

Dependent claims

A computer system, comprising:

a system controller;
a multiplicity of sub-systems coupled to the system controller;
a main memory coupled to said system controller;
and
a datapath, coupled to said system controller, interconnecting said main memory and said sub-systems in accordance with interconnect control signals received from said system controller;
a plurality of said sub-systems comprising data processors, at least one of said data processors having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one Etag for each data block stored by said cache memory;
at least one of said sub-systems including a port that transmits and receives data as data packets of a fixed size equal in size to said each data block;
said datapath and each said port having a datapath width smaller than said each data block;
said at least one of said data processors including a master interface, coupled to said system controller, for sending memory transaction requests to said system controller and for receiving cache access requests from said system controller corresponding to memory transaction requests by other ones of said data processors;
said system controller including memory transaction request logic for processing each said memory transaction request by a requesting one of said data processors, for determining which one of said cache memories and main memory to couple to the requesting data processor, for sending corresponding interconnect control signals to said datapath so as to couple the requesting data processor to said determined one of said cache memories and main memory, and for sending a reply message to said requesting data processor to prompt said requesting data processor to transmit/receive one data packet to/from said determined one of said cache memories and main memory.

7 more elements

A method for operating a cache coherent multiprocessor system having a system controller coupled to a main memory and to a plurality of data processors at least one of which has a cache memory, comprising the steps of:

storing master cache tags (Etags) in said at least one of said data processors, including one Etag for each cache line in said cache memory, said Etag for each cache line storing an address index and an Etag state value that indicates whether a data block stored in said cache line includes data modified its respective data processor;
sending memory transaction requests from said data processors to said system controller, said memory transaction requests including read requests and write requests;
each memory transaction request specifying an address for an associated data block to be read or written;
at said at least one of said data processors, receiving cache access requests from said system controller corresponding to memory transaction requests by other ones of said data processors;
providing a datapath that interconnects said main memory and said sub-systems in accordance with interconnect control signals from said system controller;
at each of said data processors, transmitting and receiving data as data packets of a fixed size equal in size to said each data block;
said datapath and each said port having a datapath width smaller than said each data block;
and
at said system controller, while processing a memory transaction request from a requesting one of said data processors, determining which one of said cache memories and main memory to couple to the requesting data processor, sending corresponding interconnect control signals to said datapath so as to couple the requesting data processor to said determined one of said cache memories and main memory, and sending a reply message to said requesting data processor to prompt said requesting data processor to transmit/receive one data packet to/from said determined one of said cache memories and main memory.

6 more elements

Dependencies are inferred from the claim text.