US 5,634,067 AGranted

Systolic array processor

AssigneesG.D.S. Co., Ltd., Yasuo Nagazumi

InventorYasuo Nagazumi

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Abstract

A systolic array processor is provided which is adapted to virtually constitute a number of analog type pipelining processors which operate in a parallel manner on an analog type shift register array such as a CCD or the like. The processor is composed of a plurality of signal processors for performing signal processings for a plurality of signals including an analog signal or signals supplied as input signals thereto and determining analog outputs, a shift register array or shift register mesh consisting of a plurality of shift registers, and a timing controller for controlling signal processings, arithmetic additions, shift operations and sequences in time of control for shift directions, of the shift registers. The shift register array or mesh includes analog shift registers having functions of performing the addition of input signals, and the analog outputs are supplied to the analog shift registers as one input signals thereof, respectively.

Claims16

Dependent claims

A systolic array processor comprising:

a plurality of signal processors each of which receives one analog signal and one digital signal, performs signal processing on the analog signal and the digital signal and outputs a result of the signal processing as an analog output signal;
a shift register mesh, including at least two groups of shift registers, a first group of shift registers being arranged orthogonally to a second group of shift registers, each of the first group and second group of shift registers including plural analog shift registers arranged linearly, each analog shift register having a plurality of analog memories, each of which has an analog signal stored therein,
said shift register mesh adding the analog signal stored in each of the plurality of analog memories and an analog signal output from at least one specified signal processor among said plurality of signal processors and storing a result of each add operation in each of the plurality of analog memories, and sequentially shifting the added analog signal stored in each of the plurality of analog memories;
wherein the plurality of analog memories of each said analog shift register make up a charge transfer device;
and
a timing controller for controlling the signal processing of said plurality of signal processors, the adding, and the shifting to control a shifting direction of said at least two groups of shift registers.

3 more elements

Dependencies are inferred from the claim text.