US 5,634,065 A · Three input arithmetic logic unit with controllable shifter and mask generator

Abstract

A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.

Claims106

Dependent claims

A data processing apparatus comprising:

an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed Boolean and arithmetic combination performing a Boolean function prior to performing an arithmetic function;
a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
a second data source supplying a second multibit digital signal;
a shifting means having a data input connected to said second data source, a shift control input receiving a shift control signal, and a data output connected to said second data input of the arithmetic logic unit, said shifting means shifting said second multibit digital signal an amount corresponding to said shift control signal and supplying said shifted second multibit digital signal to said second data input of said arithmetic logic unit;
a third data source supplying a third multibit digital signal;
and
a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask corresponding to said third multibit digital signal.

4 more elements

A data processing system comprising:

a data system bus transferring data and addresses;
an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
a data processor circuit connected to said data system bus, said data processor circuit including
an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed Boolean and arithmetic combination performing a Boolean function prior to performing an arithmetic function;
a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
a second data source supplying a second multibit digital signal,
a shifting means having a data input connected to said second data source, a shift control input receiving a shift control signal, and a data output connected to said second data input of the arithmetic logic unit, said shifting means shifting said second multibit digital signal an amount corresponding to said shift control signal and supplying said shifted second multibit digital signal to said second data input of said arithmetic logic unit,
a third data source supplying a third multibit digital signal, and
a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask corresponding to said third multibit digital signal.

6 more elements

A data processing apparatus comprising:

an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a logical OR of 1) a logical AND of a first arithmetic combination of said first multibit input and said second multibit input with said third multibit input, and 2) a logical AND of a second arithmetic combination opposite to said first arithmetic combination of said first multibit input and said second multibit input with an inverse of said third multibit input;
a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
a second data source supplying a second multibit digital signal;
a shifting means having a data input connected to said second data source, a shift control input receiving a shift control signal, and a data output connected to said second data input of the arithmetic logic unit, said shifting means shifting said second multibit digital signal an amount corresponding to said shift control signal and supplying said shifted second multibit digital signal to said second data input of said arithmetic logic unit;
a third data source supplying a third multibit digital signal;
and
a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal.

4 more elements

Dependencies are inferred from the claim text.

Three input arithmetic logic unit with controllable shifter and mask generator

Life of this patent

Three input arithmetic logic unit with controllable shifter and mask generator

Life of this patent

Abstract

Claims106