Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided

A data processing system, comprising:

• instruction fetch means for performing a fetch operation to fetch an instruction to be executed and transmitting a first enable signal of a first level indicating successful completion of the fetch operation and for transmitting the first enable Signal of a second level indicating that the fetch operation has failed;
• a programmable logic array for decoding the instruction transferred from the instruction fetch means,
• said PLA comprising:
• an AND plane having a plurality of input lines and a plurality of product term lines crossing the input lines;
• an OR plane having the product term lines and a plurality of output lines crossing the product term lines;
• a power source providing electrical power to the AND and OR planes;
• and
• connection control means comprising a first connection control means and a second connection control means, the first connection control means being connected to the plurality of the product term lines in the AND plane, the second connection control means being connected to the plurality of the output lines in the OR plane, for controlling the supply of the electrical power to the AND and OR planes;
• first register means for storing the first enable signal of the first level transmitted from the instruction fetch means and for transmitting the first enable signal of the first level;
• information processing means for executing an execution operation to execute the instruction decoded by the PLA and transmitting a completion signal of a first level indicating that the execution operation of the information processing means has completed;
• and
• first control means for receiving the first enable signal of the first level from the first register means and the completion signal of the first level from the information processing means, for performing a logical AND operation between the first enable signal of the first level and the completion signal of the first level, and for transmitting the first enable signal to the PLA when both the first enable signal and the completion signal, are at the first level,
• wherein the connection control means supplies the electrical power from the power source to the AND plane and the OR plane in order to enter the PLA into an active state only when the PLA receives the first enable signal of the first level transmitted from the first control means.