Integrated circuit input/output processor having improved timer capability

An apparatus comprising:

• a first timer bus;
• a second timer bus;
• a plurality of timebase select signals;
• a first timebase channel for providing a first timebase value, said first timebase channel being coupled to said plurality of timebase select signals;
• a second timebase channel for providing a second timebase value, said second timebase channel being coupled to said plurality of timebase select signals;
• a first timer bus control channel corresponding to said first timebase channel, the first timer bus control channel being used to select one of said first and second timebase channels, and if said first timebase channel is selected, for driving said first timer bus with the first timebase value, said first timer bus control channel being coupled to said first timer bus and to said plurality of timebase select signals;
• a second timer bus control channel corresponding to said second timebase channel, the second timer bus control channel being used to drive said first timer bus with the second timebase value if said second timebase channel is selected, said second timer bus control channel being coupled to said first timer bus and to said plurality of timebase select signals;
• a pin/status bus for providing pin and status information;
• a pin control channel for controlling transfer of the pin and status information on said pin/status bus;
• a first work channel, coupled to said first timer bus for receiving the first timebase value and coupled to said pin/status bus for receiving the pin and status information;
• and
• a second work channel, coupled to said second timer bus for receiving a third timebase value and coupled to said pin/status bus for receiving the pin and status information.