Microprocessor point-to-point communication

A computer system, comprising:

• a processor generating a first clock signal;
• a first clock line coupled to the processor for communicating the first clock signal;
• a first plurality of data lines coupled to the processor for communicating data from the processor;
• and
• a memory coupled to the first plurality of data lines and to the first clock line, the memory generating a second clock signal with an unknown phase relationship to the first clock signal, the memory comprising:
• a first buffer coupled to the first plurality of data lines,
• a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal,
• a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, and
• a first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal;
• wherein data from the processor is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer.

A multi-processor system, comprising:

• a first processor generating a first clock signal;
• a first clock line coupled to the first processor for communicating the first clock signal;
• a first plurality of data lines coupled to the first processor for communicating data from the first processor;
• and
• a second processor coupled to the first plurality of data lines and to the first clock line, the second processor generating a second clock signal with an unknown phase relationship to the first clock signal, the second processor comprising:
• a first buffer coupled to the first plurality of data lines,
• a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal,
• a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, and
• a first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal;
• wherein data from the first processor is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer.