Data transfer apparatus that compensates for differential signal delays
AssigneeHitachi, Ltd.
InventorsKenji Kashiwagi, Sigeru Kaneko, Toshitsugu Takekuma
Life of this patent
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Abstract
A data transfer apparatus transfers data between a source and a destination on a clock having a phase with a signal delay over a connection line taken into account to allow a plurality of destinations to capture the transfer data on the same clock timing. Optimized data transfer and high-speed data transfer are thus realized, which in turn significantly enhances the performance of the data transfer apparatus.
Claims23
A data transfer apparatus for transferring data over a signal line to a plurality of data transfer destinations, comprising:
- clock generating means for generating and outputting a plurality of clocks having different phases with respect to each other;
- clock selecting means for receiving said plurality of clocks generated by said clock generating means, and for selecting one of said clocks for output therefrom;
- and
- data sending means for receiving the selected clock and for sending the data according to the selected clock to one of said plurality of data transfer destinations.
A data transfer control apparatus for sending and receiving data over a signal line to and from a plurality of memory modules, said data transfer control apparatus comprising:
- first clock generating means for generating and outputting a first plurality of clocks having different phases with respect to each other;
- first clock selecting means for receiving said first plurality of clocks generated by said first clock generating means, and for selecting one of said first plurality of clocks for output therefrom, according to which data are to be written to a memory module;
- data sending means for receiving the selected clock and sending the data to be written according to the selected clock;
- second clock generating means for generating a second plurality of clocks having different phases with respect to each other;
- second clock selecting means for receiving said second plurality of clocks generated by said second clock generating means, and for selecting one of said second plurality of clocks, according to which data are to be read from a memory module;
- and
- data receiving means for receiving data read according to the clock selected by said second clock selecting means.
A data transfer system in which a plurality of units are connected with each other by a bus line for transferring data, each unit sending and receiving data from another unit by said bus line, said plurality of units each comprising:
- clock generating means for generating and outputting a plurality of clocks having different phases;
- clock selecting means for receiving said plurality of clocks generated by said clock generating means, and for selecting one of said plurality of clocks for output therefrom;
- and
- data sending means for sending data according to the clock selected by said clock selecting means to a receiving unit of said plurality of units other than the unit sending the data.
A data transfer apparatus for sending and receiving data over a signal line, comprising:
- a send clock determining circuit for receiving information representing an address to which send data are to be transmitted by the data transfer apparatus, and for determining a clock timing according to which the send data are to be transmitted by the data transfer apparatus based on the received information;
- a receive clock determining circuit for receiving information representing an address from which receive data are to be received by the data transfer apparatus, and for determining a clock timing according to which the receive data are to be received by the data transfer apparatus based on the received information;
- and
- a controller for receiving an external processing request and for providing an enable signal to one of the send clock determining circuit and the receive clock determining circuit in response to the external processing request.
A data transfer apparatus for transferring data over a signal line to a plurality of data transfer destinations, comprising:
- a clock generator having an output of a plurality of clocks having different phases with respect to each other;
- a clock selector having inputs that receive said plurality of clocks generated by said clock generator means, that selects one of said clocks for output therefrom;
- and
- a data sending circuit having an input that receives the selected clock, that sends the data according to the selected clock to one of said plurality of data transfer destinations.
A data transfer system in which a plurality of units are connected with each other by a bus line for transferring data, each unit sending and receiving data from another unit by said bus line, said plurality of units each comprising:
- a clock generator having an output of a plurality of clocks having different respective phases;
- a clock selector having inputs that receive said plurality of clocks generated by said clock generator means, that selects one of said clocks for output therefrom;
- and
- a data sending circuit having an input that receives the clock selected by said clock selector, that sends the data to a receiving unit of said plurality of units other than the unit sending the data.
Dependencies are inferred from the claim text.