Rationally clocked communication interface
AssigneeMassachusetts Institute of Technology
InventorsGill A. Pratt, Stephen A. Ward
Life of this patent
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Abstract
An interface controlling digital communication between synchronous systems of unequal clock frequency. A phase locked loop generates one clock F.sub.m from the other F.sub.n by locking the phase of the two clocks at a beating period. Within the beating period, a precompiled set of valid and invalid communication clock cycles for each direction of communication are scheduled into lookup tables. The lookup tables generate outputs to a Set of registers for communicating data between the systems of unequal clock frequency.
Claims14
A data processing system comprising processing units, operating at different frequencies, which communicate with each other, the system comprising:
- a master clock source for providing a master clock signal;
- a slave clock source associated with at least one of the processing units for generating a slave clock signal for the processing unit from the master clock signal, each of the processing units having communications clocked by the master clock signal or a slave clock signal generated from the master clock signal;
- a predictor associated with each of the processing units for identifying valid and invalid clock transitions according to the relationship between the slave clock signal and the master clock signal;
- and
- a communication register associated with each direction of communication between the processing units, the register being clocked by the master clock signal or the slave clock signal, the register being inhibited when a clock transition is identified as one of said invalid clock transitions by the predictor and the register being enabled when a clock transition is identified as one of said valid clock transitions by the predictor.
A method for arranging communication in a data processing system having at least two processing units of unequal clock frequency, comprising the steps of:
- providing a master clock signal;
- generating at least one slave clock signal from the master clock signal, each of the processing units having communications clocked by the master clock signal or a slave clock signal;
- identifying predefined valid and invalid periods of communicating data between the processing units, the valid and invalid periods being predefined according to a predetermined relationship of the master clock and the slave clock;
- communicating data between the processing units during said valid periods;
- and
- inhibiting communication of data between the processing units during said invalid periods.
A method for arranging communication between synchronous systems, each having clocks of unequal clock frequency, comprising the steps of:
- synchronizing the clocks together to generate one clock from the other;
- identifying predefined valid and invalid periods of the generated clock for communicating data between the systems, the valid and invalid periods being predefined according to a predetermined relationship between the synchronized clocks;
- communicating data between the systems for valid periods;
- and
- inhibiting communication between the systems for invalid periods.
Dependencies are inferred from the claim text.