Common memory protection system in a multiprocessor configuration using semaphore-flags stored at complementary addresses for enabling access to the memory
AssigneeFujitsu Limited
InventorHiroyuki Saitoh
Life of this patent
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Abstract
A common memory protection system in an apparatus having a multiprocessor configuration in which a plurality of CPUs are connected to a common RAM via a common bus, the system has a flag control section for outputting two semaphore-flag signals showing each semaphore-flag condition when the CPU checks two semaphore-flags by accessing the corresponding two semaphore-flag addresses that have complementary address values to each other, and a memory control section that allows the CPU to access any address in the common RAM via the common bus when receiving the semaphore-flag signals, both of which indicate that access to the common RAM is enabled, from the flag control section.
Claims6
A common memory protection system in an apparatus having a multiprocessor configuration in which a plurality of CPUs are connected to a common RAM via a common bus, the system comprising:
- a flag control section for outputting two semaphore-flag signals showing each semaphore-flag condition when said CPU checks two semaphore-flags by accessing the corresponding two semaphore-flag addresses that have the complementary address values to each other;
- and
- a memory control section that allows a CPU of a plurality of CPUs' to access any address in said common RAM via said common bus when receiving said semaphore-flag signals, both of which indicate that access to said common RAM is enabled, from said flag control section.
Dependencies are inferred from the claim text.