Semiconductor memory device for incrementing address at high speed in burst access

A semiconductor memory device comprising:

• a) a plurality of memory cells for storing data bits;
• b) peripheral circuits responsive to an internal address signal for selectively making said plurality of memory cells accessible;
• and
• c) an address generating system operative to change an internal address represented by said internal address signal for sequential burst accesses, and having
• c-1) a controlling circuit responsive to a first external control signal for changing a first control signal between a first level and a second level in synchronism with an external clock signal and to a second external control signal for changing a second control clock signal between a third level and a fourth level in synchronism with said external clock signal,
• c-2) a first latch circuit responsive to said first control signal of said second level for storing an external address signal indicative of an external address,
• c-3) a second latch circuit responsive to said first control signal of said second level for producing said internal address signal indicative of a first internal address from said external address, said second latch circuit storing said external address upon recovery of said first control signal to said first level,
• c-4) a counter responsive to said first control signal of said second level for setting a count signal to a first value used for producing a second internal address, and changing said count signal at every change of said second control clock signal from said third level to said fourth level,
• c-5) a calculated address producing circuit operative to produce a calculated address from said external address stored in said first latch circuit and the value of said count signal,
• c-6) a third latch circuit responsive to said second control clock signal of said third level for storing said calculated address, and
• c-7) a transfer circuit responsive to said second control clock signal of said fourth level for transferring said calculated address from said third latch circuit to said second latch circuit, thereby causing said second latch circuit to change said internal address to said calculated address.