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US 5,634,026 AGranted
Source identifier for result forwarding
AssigneeInternational Business Machines Corporation
InventorsJay G. Heaslip, Miles G. Canada
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorsJay G. Heaslip, Miles G. Canada
Estimating the term…
In a method and apparatus for result forwarding, a source operand compare circuit for a reservation station for a superscalar processor having a plurality of execution units, includes a source identifier for identifying an execution unit that will produce a needed result. The source identifier is included with a rename tag associated with a respective source operand. A multiplexor controlled by the source identifier directs the result of an execution unit to a comparator. The comparator compares the rename tag with a specific reservation station identity. As a result of this comparison, the needed data result is supplied to the respective source operand.
An apparatus for use with a system including a superscalar processor for simultaneously processing multiple instructions, a plurality of storing units each for storing a plurality of instructions and a plurality of results of said instructions, a plurality of execution units for executing said instructions and means for determining whether a first instruction of said plurality of instructions is dependent upon a result of a second instruction of said plurality of instructions;
An apparatus for a superscalar processor for processing instructions, said superscalar processor including a plurality of execution units, a reservation station including at least one operand slot for storing an operand, a plurality of registers for providing a first input to said reservation station, and a memory for providing a second input to said reservation station, said apparatus comprising:
A method for processing instructions in a superscalar processor, said superscalar processor including a plurality of execution units, a reservation station including at least one operand slot for storing an operand, a plurality of registers for providing a first input to said reservation station, and a memory for providing a second input to said reservation station, said method comprising:
Dependencies are inferred from the claim text.
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Dependency mechanisms, e.g. register scoreboarding: register renaming
Concurrent instruction execution, e.g. pipeline or look ahead: operand accessing
Concurrent instruction execution, e.g. pipeline or look ahead: using a plurality of independent parallel functional units
Computing and data processing
Term ended 12 May 2015 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention generally relates to a superscalar processor (e.g., a processor capable of executing two or more instructions at a time) design for a computing apparatus and specifically to a superscalar processor for following and processing multiple instructions simultaneously.
More specifically, the invention is directed to a register renaming device which resolves inter-instruction operand dependencies within a superscalar processor. To achieve such an object, the invention provides a "source identifier" with a rename tag which reduces the number of compare operations needed in such a system and attendantly decreases chip size and increases chip speed and efficiency.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is block diagram of an overall exemplary system which incorporates the comparator structure of a reservation station according to the invention.
FIG. 2 is a block diagram of a source operand comparator circuit of a reservation station according to the present invention and illustrates the instruction flow according to the present invention.
Referring now to the drawings, and more particularly to FIG. 1, a block diagram of an overall exemplary system is shown which incorporates the source operand comparator circuit structure for a reservation station according to the present invention.
As shown in FIG. 1, instructions are stored in an instruction cache 11. Instructions are read from the instruction cache 11 under control of a fetch unit (not shown). After being decoded by an instruction decode unit 12, an instruction is evaluated by a rename content addressable memory (CAM) circuit 18.
The circuitry for the cache 11, the decode unit 12, rename registers 15 (discussed below) and the rename CAM circuit 18 is believed to be well-known to one of ordinary skill in the art within the purview of this application. Thus, for brevity, such circuitry will not be described herein.