US 5,634,025 AGranted

Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units

AssigneeInternational Business Machines Corporation

InventorMauricio Breternitz, Jr.

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Abstract

In a data processing system, a plurality of primary and secondary prefetch elements are provided for prefetching a primary portion and a secondary portion of instruction words from a group of primary and secondary memory arrays coupled to each primary and secondary prefetch element, respectively. In response to a selected primary or secondary prefetch element receiving a prefetch token, the selected primary or secondary prefetch element sequentially recalls instruction words from the group of primary or secondary memory arrays, respectively. In response to a forthcoming conditional branch instruction, a plurality of prefetch elements may initiate instruction fetching so that the proper instruction may be executed during the cycle time immediately following the conditional branch instruction. The primary prefetch elements are utilized to fetch a primary portion of a variable-width instruction word, and the secondary prefetch elements, which are synchronized with the primary prefetch elements, are utilized to fetch a secondary portion of the variable-width instruction word. Program memory space is conserved by fetching the secondary portion of an instruction word only when required.

Claims16

Dependent claims

A method for efficiently executing instructions in a central processing unit of a data processing system, said method comprising the steps of:

providing M primary prefetch elements for prefetching a primary portion of an instruction word;
providing M' secondary prefetch elements for prefetching a secondary portion of an instruction word;
coupling a group of N primary memory banks to each one of said M primary prefetch elements;
coupling a group of N' secondary memory banks to each one of said M' secondary prefetch elements;
sequentially storing said primary portions of a plurality of said instruction words in each group of N primary memory banks;
sequentially storing said secondary portions of a plurality of said instruction words in each group of N' secondary memory banks;
in response to a selected primary prefetch element receiving a prefetch token, sequentially fetching said primary portions of said plurality of instruction words from said group of N primary memory banks utilizing said selected primary prefetch element;
in response to a selected secondary prefetch element receiving a prefetch token, sequentially fetching said secondary portions of said plurality of instruction words from said group of N' secondary memory banks utilizing said selected secondary prefetch element;
only in response to said selected secondary prefetch element fetching said secondary portion of said instruction word, concatenating said primary portion of said instruction word with said secondary portion of said instruction word to form an extended instruction word comprising said primary portion of said instruction word and said secondary portion of said instruction word;
and
sequentially executing said fetched plurality of instruction words and extended instruction words utilizing said central processing unit in said data processing system.

8 more elements

A system for efficiently executing instructions in a central processing unit of a data processing system comprising:

a central processing unit for executing instructions, said instructions having a primary portion and a secondary portion;
a plurality of primary memory banks for storing said primary portion of said instructions;
a plurality of secondary memory banks for storing said secondary portion of said instructions;
an instruction bus coupled to said central processing unit for transferring said primary and secondary portions of said instructions to said central processing unit;
a control bus coupled to said central processing unit for transferring control data;
a plurality of primary prefetch elements, each of said plurality of primary prefetch elements coupled to a subgroup of said plurality of primary memory banks, to said instruction bus, and to said control bus, each of said plurality of primary prefetch elements for fetching said primary portion of said instructions from said subgroup of said plurality of primary memory banks and transferring said primary portion of said instructions to said instruction bus in response to receiving said control data via said control bus or said instruction bus;
and
a plurality of secondary prefetch elements, each of said plurality of secondary prefetch elements coupled to a subgroup of said plurality of secondary memory banks, to said instruction bus, and to said control bus, each of said plurality of secondary prefetch elements for fetching said secondary portion of said instructions from said subgroup of said plurality of secondary memory banks and transferring said secondary portion of said instructions to said instruction bus in response to receiving said control data via said control bus or said instruction bus.

5 more elements

A system for efficiently executing instructions in a central processing unit of a data processing system comprising:

a central processing unit for executing instructions, said instructions having a primary portion and a secondary portion;
a plurality of primary memory banks for storing said primary portion of said instructions;
a plurality of secondary memory banks for storing said secondary portion of said instructions;
an instruction bus coupled to said central processing unit for transferring said instructions to said central processing unit;
a control bus coupled to said central processing unit for transferring control data;
a plurality of primary prefetch elements, each of said plurality of primary prefetch elements coupled to a subgroup of said plurality of primary memory banks, to said instruction bus, and to said control bus;
and
a plurality of secondary prefetch elements, each of said plurality of secondary prefetch elements coupled to a subgroup of said plurality of secondary memory banks, to said instruction bus, and to said control bus;
wherein said plurality of secondary prefetch elements are each operable in a plurality of modes including:
(a) an idle mode wherein said secondary prefetch element waits for said control data before fetching said secondary portion of said instructions from said subgroup of said plurality of secondary memory banks;
(b) a fetching mode wherein said secondary prefetch element fetches said secondary portion of said instructions from said subgroup of said plurality of secondary memory banks in response to receiving said control data;
(c) a ready mode wherein said secondary prefetch element has fetched said secondary portion of said instructions from said subgroup of said plurality of secondary memory banks and is waiting to receive said control data via said control bus or said instruction bus before transferring said secondary portion of said instructions to said central processing unit via said instruction bus;
and
(d) an active mode wherein said secondary prefetch element transfers said secondary portion of said instructions to said central processing unit via said instruction bus in response to receiving said control data via said control bus or said instruction bus.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/228,973Filed 18 Apr 1994 · continuation in part
Priority: 9 Dec 1993
Granted: 27 May 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3814
Instruction prefetching: implementation provisions of instruction buffers, e.g. prefetch buffer; banks
G06F 9/30061
To perform operations for flow control: multi-way branch instructions, e.g. CASE
G06F 9/3802
Concurrent instruction execution, e.g. pipeline or look ahead: instruction prefetching
G06F 9/3804
Instruction prefetching: for branches, e.g. hedging, branch folding