Semiconductor process, power supply voltage and temperature compensated integrated system bus termination

A computer system comprising:

• at least one central processing unit, said central processing unit comprising;
• a first plurality I/O driver/receiver cells coupled to corresponding signal lines from said central processing unit, each cell comprising:
• a bus driver circuit having an output terminal;
• a bus receiver circuit having an input terminal connected to the output terminal of the bus driver circuit;
• and
• termination means, responsive to a voltage reference signal representative of a desired impedance value of an external resistor, for providing a desired termination impedance corresponding to said desired impedance value at the common connection of the driver circuit and receiver circuit including means, responsive to changes in said desired impedance value during operation, for accordingly adjusting said desired termination impedance;
• at least one memory device said memory device comprising:
• a second plurality I/O driver/receiver cells coupled to corresponding signal lines from said memory device, each cell comprising:
• a bus driver circuit having an output terminal;
• a bus receiver circuit having an input terminal connected to the output terminal of the bus driver circuit;
• and
• termination means, responsive to a voltage reference signal representative of said desired impedance value, for providing the desired termination impedance at the common connection of the driver circuit and receiver circuit, including means, responsive to changes in said desired impedance value during operation, for accordingly adjusting said desired termination impedance;
• a plurality of conductors with each of said second plurality of I/O cells being coupled to a corresponding one of said first plurality of I/O cells by a corresponding one of said plurality of conductors;
• and
• means, responsive to an activity level of said driver, for selectively enabling said termination means.

A bus interface circuit, comprising:

• an I/O cell, said cell comprising:
• a bus driver circuit having an output terminal;
• a bus receiver circuit having an input terminal connected to the output terminal of the bus driver circuit;
• termination means, responsive to a voltage reference signal representative of a desired impedance value, for providing the desired termination impedance at the connection of the driver circuit and receiver circuit, including means, responsive to changes in said desired impedance value during operation, for accordingly adjusting said desired termination impedance;
• and
• means, responsive to a control signal for turning off said termination means when said driver is active and driving a signal from said driver and for turning on said termination means when said driver is inactive and not driving a signal from said driver.