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US 5,634,013 AGranted
Bus bridge address translator
AssigneeApple Computer, Inc.
InventorsBrian A. Childers, Eric A. Baden
Life of this patent
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AssigneeApple Computer, Inc.
InventorsBrian A. Childers, Eric A. Baden
Estimating the term…
A computer bus bridge interconnects first and second buses, the first bus being big-endian and the second bus being little-endian. First address and size signals received from the first bus during a first bus cycle are converted into second address and data unit enable signals for transmission on the second bus during a second bus cycle. The first address comprises a low-order address portion and a remaining upper-order address portion. The data unit enable signals are generated from the low-order address portion and the size signals of the first bus. An address offset is generated from the data unit enable signals. The remaining upper-order address portion of the first address are then concatenated with the address offset and a predetermined lower address portion for use as the second address. The data unit enable signals may designate, say, up to 4 possible data bytes being transferred during a single beat on the second bus. The size signals may designate, say, up to 8 possible contiguous data units being transferred during a single beat on the first bus. Here, byte enable signals are generated by first generating 8 temporary byte enable signals from the low-order address portion and the size signals. Then, 4 of the 8 temporary byte enable signals are selected for use as the byte enable signals on the second bus. The address offset is generated based on presence or absence of assertion of 4 lowest order ones of the 8 temporary byte enable signals.
In a computer bus bridge for interconnecting first and second buses, the first bus having a first endian characteristic and the second bus having a second endian characteristic that is opposite that of the first endian characteristic, an apparatus for converting first address and size signals received from the first bus during a first bus cycle into second address and data unit enable signals for transmission on the second bus during a second bus cycle, wherein each data unit enable signal is for alternatively designating presence or absence of a meaningful data unit, and wherein the first address comprises a low-order address portion and a remaining upper-order address portion, the apparatus comprising:
In a computer bus bridge for interconnecting first and second buses, the first bus having a first endian characteristic and the second bus having a second endian characteristic that is opposite that of the first endian characteristic, an apparatus for converting first address and size signals received from the first bus during a first bus cycle into second address and data unit enable signals for transmission on the second bus during a second bus cycle, wherein each data unit enable signal is for alternatively designating presence or absence of a meaningful data unit, and wherein the first address comprises a low-order address portion and a remaining upper-order address portion, the apparatus comprising:
In a computer bus bridge for interconnecting first and second buses, the first bus having a first endian characteristic and the second bus having a second endian characteristic that is opposite that of the first endian characteristic, a method of converting first address and size signals received from the first bus during a first bus cycle into second address and data unit enable signals for transmission on the second bus during a second bus cycle, wherein each data unit enable signal is for alternatively designating presence or absence of a meaningful data unit, and wherein the first address comprises a low-order address portion and a remaining upper-order address portion, the method comprising the steps of:
In a computer bus bridge for interconnecting first and second buses, the first bus having a first endian characteristic and the second bus having a second endian characteristic that is opposite that of the first endian characteristic, a method of converting first address and size signals received from the first bus during a first bus cycle into second address and data unit enable signals for transmission on the second bus during a second bus cycle, wherein each data unit enable signal is for alternatively designating presence or absence of a meaningful data unit, and wherein the first address comprises a low-order address portion and a remaining upper-order address portion, the method comprising the steps of:
Dependencies are inferred from the claim text.