Three phase clocking for an IC shift register at the end of a long serial data path

An integrated circuit comprising:

• a source of digital data and an associated original dock signal both located within a first location within the integrated circuit;
• a shift register located at a second location within the integrated circuit that is distant from the first location and that has a data input for receiving digital data and that also has respective inputs for receiving first, second and third phased clock signals;
• a digital data path coupling the source of digital data to the data input of the shift register;
• a three phase clock circuit located proximate the shift register and having a clock input for receiving the original clock signal, and also having first, second and third phased clock signal outputs at which are produced respective first, second and third phased clock signals coupled to the shift register, a transition in the original clock signal producing a subsequent delayed transition in the first phased clock signal, a subsequent doubly delayed transition in the second phased clock signal and a subsequent doubly delayed transition in the third phased clock signal, these subsequent transitions in the first and third phased clock signals being in the same direction and opposite that in the second phased clock signal, and each of these subsequent transitions being in their respective opposing directions when the transition in the original clock signal is in its opposite direction;
• and
• an original clock signal path coupling the original clock signal to the clock input of the three phase clock circuit.