Phase locked loop for high speed data capture of a serial data stream

A system for data capture and clock recovery of a serial data stream, comprising:

• a data input for receiving the serial data stream;
• a multiple-bit latch having a plurality of designated data and boundary-detect latch elements, with each latch element comprising a latch input coupled to the data input, a sample clock input, and a latch output;
• a multiple-stage voltage controlled oscillator having a voltage control input, a plurality of sample clock outputs, and an adjustable delay between each sample clock output, wherein each sample clock output is coupled to a corresponding sample clock input;
• a phase detection circuit having phase detect inputs coupled to the latch outputs and having a phase control output;
• a phase locked feedback loop coupled between the phase control output and the voltage control input;
• and
• a data recovery storage element having a plurality of data recovery inputs which are coupled to respective latch outputs of the designated data latch elements and having a recovery clock input which is coupled to one of the plurality of sample clock outputs.

A method of locking onto a phase and frequency of a serial input signal, comprising:

• applying the serial input signal to a multiple-bit latch comprising a boundary detect latch element, a previous in time data latch element and a subsequent in time data latch element, wherein each latch element comprises a latch output;
• generating a first sample clock, a second sample clock which is delayed from the first sample clock by a delay, and a third sample clock which is delayed from the second sample clock by the delay;
• operating the previous data latch element with the first sample clock, the boundary-detect latch element with the second sample clock and the subsequent data latch element with the third sample clock;
• decreasing the delay if the latch outputs of the previous in time data latch element and the boundary-detect latch element have different logic states;
• and
• increasing the delay if the latch outputs of the boundary-detect latch element and the subsequent in time data latch element have different logic states.