Digital signal processor optimized for decoding a signal encoded in accordance with a Viterbi algorithm

A method of decoding a received digital signal encoded in accordance with a Viterbi algorithm by a digital signal processor, wherein said method of decoding calculates a first pair of binary signals C.sub.2n and C.sub.2n+1 based upon a second pair of binary signals C.sub.n and C.sub.n+m/2 and a transitional signal, a, in accordance with

• C.sub.2n =minimum (C.sub.n +a, C.sub.n+m/2 -a)
• C.sub.2n+1 =minimum (c.sub.n -a, C.sub.n+m/2 +a)
• wherein said digital signal processor comprising:
• a first and a second data bus means for supplying simultaneously a first and a second plurality of binary signals, respectively;
• a first and a second shifter means each for receiving simultaneously a first input signal, and for generating a third plurality of binary signals, respectively;
• first means for supplying said first plurality of binary signals to said first shifter means as said first input signal;
• a first multiplexer means;
• said first multiplexer means for receiving said first and said second plurality of binary signals from said first and second data bus means and for supplying either said first or said second plurality of binary signals to said second shifter means;
• a first and a second Arithmetic Logic Unit (hereinafter:
• "ALU") means, each for receiving a second and a third input signal and for generating an output signal, said output signal representative of said second input signal added to or subtracted by said third input signal;
• second means for supplying said third plurality of binary signals from said first and second shifter means simultaneously as said third input signal to said first and second ALU means, respectively;
• a first and a second accumulator means for receiving simultaneously said output signals from said first and second ALU means, respectively, for storing said output signals and for supplying same as said fourth input signals to said first and second ALU means, respectively;
• minimum determining means for receiving said output signals from said first and second accumulator means, for comparing same, and for selecting the lesser of said output signals stored in said first and second accumulator means and for generating a fifth plurality of binary signals in response thereto;
• and
• third accumulator means for receiving and for storing said fifth plurality of binary signals;
• and
• wherein said method comprising
• a) supplying simultaneously said second pair of binary signals C.sub.n and C.sub.n+m/2 from said first and second data bus means, respectively, through said first and second shifter means, respectively, through said first and second ALU means;
• storing said second pair of binary signals C.sub.n and C.sub.n+m/2 simultaneously in said first and second accumulator means, respectively;
• b) supplying said transition signal a from said first data bus means simultaneously to both said first and second shifter means and simultaneously to said first and second ALU means respectively;
• calculating
• C.sub.n +a
• by said first ALU means and generating an output signal in response thereto;
• calculating
• C.sub.n+m/2 -a
• by said second ALU means and generating an output signal in response thereto, simultaneous with the calculation of C.sub.n +a by said first ALU means;
• storing said output signals of said first and second ALU means simultaneously in said first and second accumulator means;
• determining the lesser of said output signals (C.sub.n +a and C.sub.n+m/2 -a) stored in said first and second accumulator means respectively by said minimum determining means;
• storing said fifth plurality of binary signals from said minimum determining means, in said third accumulator means;
• c) shifting said transition signal a from said first data bus means, by said first and second shifter means, by one binary digit to generate simultaneously a shifted signal of 2a from said first and second shifter means;
• supplying said shifted signal 2a simultaneously to said first and second ALU means, respectively;
• calculating
• C.sub.n 30 a-2a
• by subtracting the shifted signal 2a from the output signal stored in said first accumulator mans, by said first ALU means and generating an output signal in response thereto;
• calculating
• C.sub.n+m/2 -a+2a
• by adding the shifted signal 2a to the output signal stored in said second accumulator means, by said second ALU means and generating an output signal in response thereto, simultaneous with the calculation of C.sub.n +a-2a by said first ALU means;
• storing said output signals of said first and second ALU means simultaneously in said first and second accumulator means;
• and
• determining the lesser of said output signals (C.sub.n -a and C.sub.n+m/2 +a) stored in said first and second accumulator means respectively by said minimum determining means.