Error detection and correction circuit

An improved error detection and correction circuit for use with a device for detecting errors in stored check bits and providing an output enable signal on detection of such errors, said correction circuit comprising:

• first means for providing a data word and a first set of check bits;
• second means for generating a second set of check bits corresponding to said data word;
• third means for outputting syndrome bits in response to the generated second set of check bits and the first set of check bits and for detecting an error in the first set of check bits;
• and
• fourth means for storing said second set of check bits and selectively outputting said second set of check bits in response to said enable signal on the detection of the error in the first set of check bits, wherein the output of said fourth means is provided to said first means, thereby correcting check bit errors.

An improved error detection and correction circuit comprising:

• a check bit generator which receives a data word and outputs generated check bits in response thereto;
• a syndrome generator which receives as inputs said generated check bits from said check bit generator and stored check bits and outputs syndrome bits in response thereto;
• an error detector which receives as input said syndrome bits from said syndrome generator, decodes said syndrome bits to detect an error in said bit data word or in said stored check bits, and outputs an indication of the presence of the error;
• a check bit output latch which receives as inputs said generated check bits from said check bit generator and selectively outputs said generated check bits on the detection of the error in the stored check bits for correcting stored check bit errors;
• and
• an error corrector which receives as inputs said syndrome bits from said syndrome generator and said data word and outputs a corrected data word.