Method for integrated circuit design and test

A method for testing an integrated circuit using a tester, the tester having regularly recurring internal periods for timing reference, said internal periods being synchronous with a clock signal of said integrated circuit, the integrated circuit having one or more signal input ports, one or more signal output ports and a logic circuit disposed between the input ports and the output ports, wherein an input signal applied to one or more of the input ports results, from the operation of the logic circuit, in an output signal appearing at one or more of the output ports, comprising the steps of:

• selecting a first output port to use as a reference port;
• determining whether a predetermined signal event occurs at said first output port during a predetermined time range;
• and
• if said predetermined signal event occurs at said first output port during said predetermined time range, using said predetermined signal event as a timing reference for a test event of said integrated circuit, said test event occurring a predetermined time interval from said predetermined event.

A method for testing an integrated circuit using a tester, the tester having regularly recurring internal periods for timing reference, said internal periods being synchronous with a clock signal of said integrated circuit, the integrated circuit having one or more signal input ports, one or more signal output ports and a logic circuit disposed between the input ports and the output ports, wherein an input signal applied to one or more of the input ports results, from the operation of the logic circuit, in an output signal appearing at one or more of the output ports, comprising the steps of:

• selecting a first output port having a first predetermined signal event that occurs at said first output port during a first predetermined time range, said first predetermined time range being determined with respect to said internal period;
• selecting a second output port having a second predetermined signal event that occurs at said first output port during a second predetermined time range, said second predetermined time range being determined with respect to said internal period;
• using said first predetermined signal event as a first timing reference for a first test event of said integrated circuit, said first test event occurring a first predetermined time interval from said first predetermined event;
• and
• using said second predetermined signal event as a second timing reference for a second test event of said integrated circuit, said second test event occurring a second predetermined time interval from said second predetermined event.

A method for testing an integrated circuit using a tester, the tester having regularly recurring internal periods for timing reference, said internal periods being synchronous with a clock signal of said integrated circuit, the integrated circuit having one or more signal input ports, one or more signal output ports and a logic circuit disposed between the input ports and the output ports, wherein an input signal applied to one or more of the input ports results, from the operation of the logic circuit, in an output signal appearing at one or more of the output ports, comprising the steps of:

• selecting a first output port to use as a first reference port;
• selecting a second output port to use as a second reference port;
• determining whether a first predetermined signal event occurs at said first output port during a first predetermined time range;
• determining whether a second predetermined signal event occurs at said second output port during a second predetermined time range;
• if said first predetermined signal event occurs at said first output port during said first predetermined time range, using said first predetermined signal event as a timing reference for a first test event of said integrated circuit, said first test event occurring a first predetermined time interval from said first predetermined event
• if said first predetermined signal event occurs at said first output port during said first predetermined time range, using said first predetermined signal event as a timing reference for a first test event of said integrated circuit, said first test event occurring a first predetermined time interval from said first predetermined event;
• and
• if said second predetermined signal event occurs at said second output port during said second predetermined time range, using said second predetermined signal event as a timing reference for a second test event of said integrated circuit, said second test event occurring a second predetermined time interval from said second predetermined event.

A method for generating one or more test vectors usable for testing an integrated circuit using a tester, the tester having regularly recurring internal periods for timing reference, said internal periods being synchronous with a clock signal of said integrated circuit, the integrated circuit having one or more input signals, one or more output signals and a logic circuit disposed between the input signals and the output signals, wherein an input signal results, from the operation of the logic circuit, in an output signal, comprising the steps of:

• providing a vector generator, the vector generator receiving as an input one or more simulation trace files and providing as an output one or more test vectors;
• providing a template file to the vector generator, the template file identifying a dynamic reference point output signal and a signal to be tested;
• causing the vector generator to, in response to the template file, determine a time, relative to the internal period at which the reference point output signal occurs;
• causing the vector generator to generate a file including one or more test vectors for the test of the signal to be tested, and including an offset value representing a time interval from the dynamic reference point output signal at which the test of the signal to be tested is to be done.

A method for testing an integrated circuit using a tester, the tester having internal periods for timing reference, the integrated circuit having one or more input ports, one or more output ports and a logic circuit disposed between the input ports and the output ports, wherein the tester applies an input signal to one or more of the input ports, the input signal being synchronous to the internal periods of the tester, such that, by the operation of the logic circuit, an output signal appears at one or more of the output ports, comprising the steps of:

• selecting a first output port having a predetermined signal event that occurs at said first output port during a predetermined time range, said predetermined time range being determined with respect to said internal period;
• using said predetermined signal event as a timing reference for one or more test events of said integrated circuit, said test event occurring a predetermined time interval from said predetermined event;
• and
• using said internal periods as alternate timing references for test events.

A method for testing an integrated circuit using a tester, the tester having internal periods for timing reference, the integrated circuit having one or more input ports, one or more output ports and a logic circuit disposed between the input ports and the output ports, wherein the tester applies an input signal to one or more of the input ports, the input signal being synchronous to the internal periods of the tester, such that, by the operation of the logic circuit, an output signal appears at one or more of the output ports, comprising the steps of:

• selecting a first output port having a first predetermined signal event that occurs at said first output port during a first predetermined time range, said first predetermined time range being determined with respect to said internal period;
• and
• using said first predetermined signal event as a first timing reference for a first test event of said integrated circuit, said first test event occurring a first predetermined time interval from said first predetermined event;
• selecting a second output port having a second predetermined signal event that occurs at said second output port during a second predetermined time range, said second predetermined time range being determined with respect to said internal period;
• and
• using said second predetermined signal event as a second timing reference for a second test event of said integrated circuit, said second test event occurring a second predetermined time interval from said second predetermined event.