Programmable built-in self test method and controller for arrays
AssigneeInternational Business Machines Corporation
InventorsPhilip G. Shephard, III, William V. Huott, Paul R. Turgeon, Robert W. Berry, Jr., Gulsun Yasar, Frederick J. Cox, Pradip Patel, Joseph B. Hanley, III
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Abstract
An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy.
Claims18
A built-in, on-chip test system for testing an array having data input ports, data output ports, and address ports, comprising in combination:
- a data control register for generating and applying deterministic data patterns to the data input ports of said VLSI array;
- an address control register for generating addresses for application to said array chip in coordination with said data control register;
- a comparator for comparison of data inputted to said data input ports of said VLSI array from said data control register with data outputted from said data output ports of said VLSI array;
- a memory array for storing a plurality of microcode control vectors, each vector including a data control register field, an address control register field, the microcode pointer control register field and a read/write enable control field;
- a microcode pointer control register and finite state machine for means controlling said address control register, said data control register and said microcode pointer control register in response to said plurality of microcode control vectors and to an overflow feedback state of said data control register and said address control register.
Dependencies are inferred from the claim text.