Echo canceler
AssigneeSiemens Schweiz AG
InventorsPeter Gysel, Bruno Wenger, August Kalin, Daniel Muller
Life of this patent
Estimating the term…
Abstract
Echo canceler. A circuit arrangement for the cancellation of echo signals, wherein in the received path, an analog/digital converter is connected with a first adder and a second adder is interposed after the analog/digital converter, with the estimated echo signal being divided into first and second portions, whereby the first portion is transmitted to the first adder and the second portion is transmitted to the second adder for the production of the received signal. In a further embodiment, a third adder is interposed between the analog/digital converter and the second adder, via which the output signal of a compensation filter is added to the signal in the received path.
Claims13
A circuit arrangement comprising:
- a send path carrying a send signal;
- a receiving path carrying a received signal;
- an adaptive filter;
- an analog first adder;
- a first digital/analog converter;
- a transmission unit;
- and
- a two line wire attached to the transmission unit,
- wherein over the two line wire at least the send signal, the received signal and echo signal portions are transmitted, the send path and the received path are connected with the transmission unit and the send signal is transmitted to the adaptive filter for providing an estimated echo signal, the estimated echo signal transmitted through the first digital/analog converter to the first analog adder, located in the received path, for the reduction of an echo signal portion in the received signal,
- wherein the first adder, viewed in a direction of transmission, is followed by an analog/digital converter and then by a digital second adder, and a first portion of the estimated echo signal being transmitted to the first adder and a second portion of the estimated echo signal being transmitted to the second adder, for the production of the received signal,
- wherein means for full utilization of the dynamic range are provided for the analog/digital converter and therefore for the automatic adaptation to differing lengths of the two line wire,
- the means for full adaptation to differing line lengths comprising:
- a bit shift unit;
- an amplifier unit;
- and
- a received signal measuring unit, the bit shift unit being provided upstream of the second adder in the signal transmission direction;
- the amplifier unit being provided between the first adder and the analog/digital converter and the received signal measuring unit impressed with the received signal for the control of the bit shift unit and the amplifier unit.
A circuit arrangement comprising:
- a send path carrying a send signal;
- a receiving path carrying a received signal;
- an adaptive filter;
- an analog first adder;
- a first digital/analog converter;
- a transmission unit;
- and
- a two line wire attached to the transmission unit,
- wherein over the two line wire at least the send signal, the received signal and echo signal portions are transmitted, the send path and the received path are connected with the transmission unit and the send signal is transmitted to the adaptive filter for providing an estimated echo signal, the estimated echo signal transmitted through the first digital/analog converter to the first analog adder, located in the received path, for the reduction of an echo signal portion in the received signal,
- wherein the first adder, viewed in a direction of transmission, is followed by an analog/digital converter and then by a digital second adder, and a first portion of the estimated echo signal being transmitted to the first adder and a second portion of the estimated echo signal being transmitted to the second adder, for the production of the received signal,
- wherein means for full utilization of the dynamic range are provided for the analog/digital converter and therefore for the automatic adaptation to differing lengths of the two line wire
- the means for adaptation onto differing line lengths comprising an adjustable amplifier and a detector,
- the adjustable amplifier, viewed in a signal transmission direction, is provided upstream of the first adder and the detector is impressed with the output signal of the analog/digital converter for the control of the adjustable amplifier.
A circuit arrangement comprising:
- a send path carrying a send signal;
- a receiving path carrying a received signal;
- an adaptive filter;
- an analog first adder;
- a first digital/analog converter;
- a transmission unit;
- and
- a two line wire attached to the transmission unit,
- wherein over the two line wire at least the send signal, the received signal and echo signal portions are transmitted, the send path and the received path are connected with the transmission unit and the send signal is transmitted to the adaptive filter for providing an estimated echo signal, the estimated echo signal transmitted through the first digital/analog converter to the first analog adder, located in the received path, for the reduction of an echo signal portion in the received signal,
- wherein the first adder, viewed in a direction of transmission, is followed by an analog/digital converter and then by a digital second adder, and a first portion of the estimated echo signal being transmitted to the first adder and a second portion of the estimated echo signal being transmitted to the second adder, for the production of the received signal,
- the adaptive filter comprising at least one of a FIR (Finite Impulse Response) filter portion (FIR) and an IIR (Infinite Impulse Response) filter portion (IIR), the FIR filter portion of the storage compensation type,
- a second digital/analog converter and a send signal filter provided in the send path, with the send signal filter being input-connected with the digital/analog converter and output-connected with the transmission unit, the digital/analog converter impressed with the send signal,
- the send signal filter produces a predetermined pulse form at the outlet of the send filter, and
- the send filter has a transfer function T(s)=T.sub.1 (s)*T.sub.2 (s,) wherein:
- ##EQU3##
A circuit arrangement comprising:
- a send path carrying a send signal;
- a receiving path carrying a received signal;
- an adaptive filter;
- an analog first adder;
- a first digital/analog converter;
- a transmission unit;
- and
- a two line wire attached to the transmission unit,
- wherein over the two line wire at least the send signal, the received signal and echo signal portions are transmitted, the send path and the received path are connected with the transmission unit and the send signal is transmitted to the adaptive filter for providing an estimated echo signal, the estimated echo signal transmitted through the first digital/analog converter to the first analog adder, located in the received path, for the reduction of an echo signal portion in the received signal,
- wherein the first adder, viewed in a direction of transmission, is followed by an analog/digital converter and then by a digital second adder, and a first portion of the estimated echo signal being transmitted to the first adder and a second portion of the estimated echo signal being transmitted to the second adder, for the production of the received signal
- the adaptive filter comprising at least one of a FIR (Finite Impulse Response) filter portion (FIR) and an IIR (Infinite Impulse Response) filter portion (IIR), the FIR filter portion of the storage compensation type,
- a second digital/analog converter and a send signal filter provided in the send path, with the send signal filter being input-connected with the digital/analog converter and output-connected with the transmission unit, the digital/analog converter impressed with the send signal
- the send signal is tetravalent and the digital/analog converter includes two bits, whereby the FIR filter portion is so adaptively adjusted that non-idealities are corrected,
- the send signal filter produces a predetermined pulse form at the outlet of the send filter, and
- the send filter has a transfer function T(s)=T.sub.1 (s)*T.sub.2 (s), wherein:
- ##EQU4##
Dependencies are inferred from the claim text.