Address buffer for blocking noise
AssigneeLG Semicon Co., Ltd.
InventorYeon-Joong Yoon
Life of this patent
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Abstract
An address buffer capable of preventing malfunctions of a memory device or preventing delay of the signal outputted from the output buffer by blocking noise, which inverts or blocks the signal outputted from the address signal input unit according to a PMOS control signal and an NMOS control signal, and latches the signal outputted from the clock inverter in the latch unit. The PMOS and the NMOS control signals are outputted to the clock inverter by logically operating the control signal outputted from the control signal generating unit according to the output signal of the latch unit, thereby blocking a noise generated in the address input unit by the signal outputted from the output buffer by the clock inverter.
Claims13
An address buffer for blocking a noise comprising:
- an address signal input means for receiving a chip selection signal and an address signal bit;
- a clock inverter means for inverting or blocking a signal outputted from the address signal input means according to an NMOS control signal and a PMOS control signal;
- a latch means for latching a signal outputted from the clock inverter means;
- a first inverter for outputting an internal address signal to an address decoder by inverting a signal outputted from the latch means;
- a second inverter for outputting an inverted internal address signal to the address decoder by inverting the internal address signal outputted from the first inverter;
- an address transition detecting means for outputting an address transition detection signal according to the signal outputted from the latch means;
- a control signal generating means for outputting a control signal generated by the signal outputted from the address transition detecting means to an output buffer;
- and
- a clock inverter control signal generating means for outputting the NMOS and PMOS control signals to the clock inverter means by delaying the control signal outputted from the control signal generating means for a predetermined time and by logically operating the delayed signal and the control signal outputted from the control signal generating means.
A buffer for a memory device comprising:
- an address signal input unit receiving a first signal and an address signal bit;
- an inverter unit coupled to said address signal input unit and being responsive to first and second control signals;
- a latch unit coupled to said inverter unit;
- an address transition detecting unit coupled to said latch unit;
- a control signal generating unit coupled to said address transition detecting unit;
- an output buffer coupled to said first control signal generating unit;
- and
- an inverter control unit coupled to said first control signal generating unit and generating said first and second control signals to control an operation of said inverter unit.
Dependencies are inferred from the claim text.