US 5,633,832 AGranted

Reduced area word line driving circuit for random access memory

AssigneeAlliance Semiconductor Corporation

InventorsVipul C. Patel, Kenneth A. Poteet, Chitranjan N. Reddy

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Abstract

A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12). The channel width of the inverter NMOS transistors (N2) are relatively large in relation to the inverter PMOS transistors (P2), allowing the NMOS transistors (N2) to be turned on by a voltage of Vcc-Vtn, where Vtn is the threshold voltage of the transfer transistors (N0).

Claims21

Dependent claims

In a semiconductor memory device having a first power supply voltage, a second power supply voltage, and a boost power supply voltage greater than the first power supply voltage, a word line driving circuit, comprising:

a decoder circuit including a select circuit having a number of active devices coupled between a decode node and the second power supply, the select circuit pulling the control node to the second power supply in response to a plurality of active decoder signals in a select operation, the decoder circuit further including a deselect circuit coupled between the first power supply and the control node, the deselect circuit pulling the control node to the first power supply in response to an active reset signal in a deselect operation;
and
a plurality of word line driver stages, each said stage including,
a transfer transistor coupled between the decode node and a control node and responsive to word line select signal, the transfer transistor coupling the first power supply voltage to its respective control node in the deselect operation,
a first driver transistor of a first conductivity type having its source coupled to the boost voltage, its drain coupled to a word line, and its gate coupled to a control node,
a second driver transistor of a second conductivity type having its source coupled to the second power supply voltage, its drain coupled to the word line, and its gate coupled the control node, and
a level shifting transistor of the first conductivity type having its source coupled to the boost voltage, its drain coupled to the control node, and its gate coupled to the word line.

4 more elements

In a random access memory having a plurality of word lines, a word line driving circuit, comprising:

a driver circuit for each word line, said driver circuit including
a CMOS inverter having a first node coupled to a boost voltage, a second node coupled to a second supply voltage, a common gate forming a control node, and an output coupled to its respective word line,
a level shifter transistor of a first conductivity type having a source coupled to the boost voltage, a drain coupled to the control node, and a gate coupled to the word line;
a decoupling transistor for each driver circuit, each said decoupling transistor having a source connected to the control node of its respective driver circuit, the drains of said decoupling transistors being connected to a common decode node, a selected decoupling transistor coupling its respective control node to the common decode node in a select operation, each said decoupling transistor coupling its respective control node to the common decode node in a deselect operation;
and
a decoder circuit intermediate the decode node and the second supply voltage, said decoder circuit coupling the decode node to the second supply voltage via at least one active device in response to a decoder address in the select operation, said decoder circuit coupling the decode node to a first power supply voltage in the deselect operation.

3 more elements

Dependencies are inferred from the claim text.