Random access memory block circuitry for programmable logic array integrated circuit devices
AssigneeAltera Corporation
InventorsChiakang Sung, Wanli Chang, Joseph Huang, Richard G. Cliff
Life of this patent
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Abstract
A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
Claims37
Memory circuitry for inclusion on a programmable logic array integrated circuit device, which includes a plurality of logic signal conductors, comprising:
- a plurality of programmable first memory cells;
- interconnection circuitry for selectively interconnecting said first memory cells in a series such that each of said first memory cells is programmable from a preceding first memory cell in said series when said first memory cell is connected to said preceding first memory cell in said series;
- a second programmable memory cell having an input terminal and an output terminal for selectively storing data applied to said input terminal and for subsequently outputting the data thus stored by said second memory cell;
- and
- input switching circuitry for selectively connecting said input terminal to said interconnection circuitry at an intermediate point Which is between two adjacent ones of said first memory cells in said series and for alternatively connecting said input terminal to a first of said logic signal conductors.
The method of programming memory on a programmable logic array integrated circuit device which includes a plurality of first memory cells that are selectively interconnectable in a series in which each of said first memory cells is programmable from a preceding first memory cell in said series, and a second memory cell that is selectively connectable to an intermediate point which is between two adjacent ones of said first memory cells in said series, said programmable logic array integrated circuit further including a plurality of logic signal conductors, said method comprising the steps of:
- applying successive programming data bits to a beginning of said series during respective successive programming time intervals;
- disconnecting a respective one of said first memory cells from said series after each of respective programming time intervals, said first memory cells being thus disconnected from said series in order progressing from an end of said series which is remote from said beginning;
- connecting said second memory cell to said intermediate point when all of said first memory cells beyond said intermediate point have been disconnected in order to program said second memory cell with programming data from said intermediate point;
- disconnecting said second memory cell from said intermediate point after programming of said second memory cell in said connecting step;
- and
- selectively connecting said second memory cell to a first one of said logic signal conductors in order to read out from said second memory cell data stored in said second memory cell.
Dependencies are inferred from the claim text.