US 5,633,829 A · Serial access memory device capable of controlling order of access to memory cell areas

Abstract

A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.

Claims24

Dependent claims

A serial access memory device, comprising:

a memory cell array having a plurality of separately accessible memory cell areas;
each said area having memory cells disposed therein to store data signals;
a plurality of access means respectively connected to corresponding memory cell areas for accessing data signals stored in memory cells of said respective memory cell areas;
a plurality of activating means each connected to a corresponding one of said plurality of access means and responsive to a clock signal for activating said corresponding one of said plurality of access means;
and
select signal storing means for storing a selecting signal and generating a plurality of control signals determined by said selecting signal;
each said activating means comprising selective coupling means responsive to said control signals generated by said select signal storing means for selectively coupling at least two of said plurality of activating means in a predetermined configuration selected for successively activating at least two corresponding access means in response to said clock signal.

4 more elements

A serial access memory device for converting first and second digital video data for progressive scan, comprising:

a memory cell array having four memory cell columns each having n memory cells disposed in k rows, where n and k are integers greater than one;
four writing means each respectively connected to a corresponding one of said four memory cell columns for writing one of the first or second video data in memory cells of said corresponding memory cell column;
first selecting means responsive to an externally applied first clock signal for alternately selecting a predetermined two of said four writing means;
said writing means selected by said first selecting means writing said first video data into memory cells of at least a first corresponding memory cell column;
second selecting means responsive to said externally applied first clock signal for alternately selecting the remaining two of said four writing means;
said writing means selected by said second selecting means writing said second video data into memory cells of at least a second corresponding memory cell column;
four reading means each respectively connected to a corresponding one of said four memory cell columns for reading stored data from memory cells therein;
and
third selecting means responsive to an externally applied second clock signal for successively selecting individual ones of said four reading means,
said second clock signal having a frequency twice that of said first clock signal, and
said reading means selected by said third selecting means respectively reading data stored in the memory cells of said memory cell column corresponding thereto.

8 more elements

A serial access memory device for delaying at least first and second serial data, comprising:

a memory cell array having m memory cell columns each having n memory cells disposed in k rows, where m, n and k are integers greater than one;
m writing means each respectively connected to a corresponding one of said m memory cell columns for writing one of the first or second serial data in memory cells of said corresponding memory cell column;
first serial selecting means responsive to an externally applied first clock signal for successively selecting a predetermined i out of said m writing means, where i is an integer,
said i writing means selected by said first serial selecting means each respectively writing said one of said first and second serial data into memory cells of a memory cell column corresponding thereto;
second serial selecting means responsive to said first clock signal for successively selecting i out of the remaining (m-i) of said m writing means,
said i writing means selected by said second serial selecting means each respectively writing the other of said first and second serial data into memory cells of a memory cell column corresponding thereto;
m reading means each respectively connected to a corresponding one of said m memory cell columns for reading stored data from memory cells in said corresponding memory cell column;
third serial selecting means synchronized with said first serial selecting means for successively selecting corresponding i reading means,
said i reading means selected by said third serial selecting means each respectively reading stored data from memory cells of the memory cell column corresponding thereto;
and
fourth serial selecting means synchronized with said second serial selecting means for successively selecting corresponding i reading means,
said reading means selected by said fourth serial selecting means each respectively reading stored data from memory cells of the memory cell column corresponding thereto.

9 more elements

A serial access memory device comprising:

a memory array having a plurality of separately accessible memory cell areas, each said area having a plurality of memory cells and bit lines connected to said plurality of memory cells;
a plurality of data lines;
a plurality of access means respectively connected between respective bit lines of a corresponding memory cell area and a corresponding data line for transferring data between said corresponding data line and said respective bit lines of said corresponding memory cell area;
a plurality of activating means each responsive to a clock signal for generating an activating signal for activating a corresponding one of said plurality of access means;
and
select signal generating means for generating a plurality of control signals;
wherein
each said activating means comprises.sub.I
first and second input terminals,
first and second output terminals,
an activating signal generating means for generating said activating signal, said activating signal generating means having an input node and an output node, and
path selecting means for selecting one of said input terminals and one of said output terminals to form a path for transfer of said activating signal between connected ones of said activating means,
said path selecting means comprising first and second switching means;
said first switching means responsive to at least one of said plurality of control signals for connecting an input node of said activating signal generating means to a selected one of said first and second input terminals;
and
said second switching means responsive to at least one of said plurality of control signals for connecting an output node of said activating signal generating means to a selected one of said first and second output terminals, whereby said activating signal is selectively transferred from a selected input terminal through said activating signal generating means to a selected output terminal.

13 more elements

Dependencies are inferred from the claim text.

Serial access memory device capable of controlling order of access to memory cell areas

Life of this patent

Serial access memory device capable of controlling order of access to memory cell areas

Life of this patent

Abstract

Claims24