US 5,633,828 A · Circuitry and methodology to test single bit failures of integrated circuit memory devices

Abstract

According to the present invention, a structure and method provides for single bit failures of an integrated circuit memory device to be analyzed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads. According to the structure of the present invention, bitline load devices of the integrated circuit memory device are controlled by a test mode signal, the state of which determines when the test mode will be entered. These bitline load devices are connected to the bitlines true and complement which in turn are connected to the memory cell. Select devices, such as column select transistors, are connected to the bitline true and bitline complement; they are also connected to driver circuitry by a bus, such as a write bus, a read bus or a write/read bus. The driver circuitry is supplied with supply voltages as well as data signals. Further, a buffer circuit allows bitlines true and bitlines complement not associated with the single bit being tested to be pulled to a logic low level. A dummy structure also provides the opportunity to directly monitor the bitlines of the integrated circuit memory device without the need for microprobing.

Claims40

Dependent claims

A method for testing single bits of an integrated circuit memory device, comprising the steps of:

entering a test mode by setting a test mode signal of the integrated circuit memory device to a first logic state;
turning off a bitline load device of a memory cell of the integrated circuit memory device, wherein the memory cell of the integrated circuit memory device is connected to the bitline which is connected to a first supply voltage through the bitline load device;
selecting, by address selection, a single bit of the memory cell of the integrated circuit memory device to be tested, wherein the bitline is associated with the single bit;
placing the integrated circuit memory device into a write mode;
setting a plurality of bitlines of the integrated circuit memory device not associated with the single bit to a second logic state, wherein the first logic state is not equal to the second logic state;
connecting the bitline associated with the single bit to a supply bus, wherein the supply bus is connected to a test pad;
and
monitoring an electrical characteristic of the single bit on the test pad.

5 more elements

A method for testing single bits of an integrated circuit memory device, comprising the steps of:

entering a test mode by setting a test mode signal of the integrated circuit memory device to be tested to a first logic state;
turning off a first bitline load device and a second bitline load device of a memory cell of the integrated circuit memory device, wherein the memory cell of the integrated circuit memory device is connected to the bitline true and the bitline complement, and the bitline true is connected to a first supply voltage through the first bitline load device and the bitline complement is connected to the first supply voltage through the second bitline load device;
selecting, by address selection, a single bit of the memory cell of the integrated circuit memory device to be tested, wherein the bitline true and the bitline complement are associated with the single bit;
placing the integrated circuit memory device into a write mode;
setting a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit to a second logic state;
connecting the bitline true and the bitline complement associated with the single bit to a supply true bus and a supply complement bus, respectively, wherein the supply true bus is connected to a first test pad and the supply complement bus is connected to a second test pad;
and
monitoring an electrical characteristic of the single bit on the first test pad and the second test pad.

5 more elements

An integrated circuit memory device structure for testing single bits of an integrated circuit memory device, comprising:

a memory cell of the integrated circuit memory device;
a first bitline load device connected to a first supply voltage and controlled by a test mode signal, wherein when the test mode signal is equal to a first logic state the integrated circuit memory device is in a test mode during which a single bit of the memory cell may be tested;
a second bitline load device connected to the first supply voltage and controlled by the test mode signal;
a wordline bus connected to the memory cell;
a bitline true connected to the first bitline load device and to the memory cell;
a bitline complement connected to the second bitline load device and to the memory cell;
a first select device connected to the bitline true and controlled by a select bus;
a second select device connected to the bitline complement and controlled by the select bus;
a first driver connected to the first select device by a true bus, wherein the first driver receives a data complement input signal and is controlled by a voltage supply true signal electrically connected to a first test pad;
a second driver connected to the second select driver by a complement bus, wherein the second driver receives a data true input signal and is controlled by a voltage supply complement signal electrically connected to a second test pad, wherein an electrical characteristic of the single bit may be monitored on the first test pad and the second test pad;
and
means for setting a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit to a second logic state during the test mode.

9 more elements

A structure for monitoring the bitline voltages of an integrated circuit memory device, comprising:

a memory cell of the integrated circuit memory device;
a bitline true connected to the memory cell;
a bitline complement connected to the memory cell;
a wordline bus connected to the memory cell;
a first select device connected to the bitline true and controlled by a select bus connected to a first supply voltage;
a second select device connected to the bitline complement and controlled by the select bus;
a first driver connected to the first select device by a true bus and connected to a second test pad, wherein the first driver receives a data complement input signal and is controlled by a voltage supply true signal;
a second driver connected to the second select driver by a complement bus and connected to a third test pad, wherein the second driver receives a data true input signal and is controlled by a voltage supply complement signal;
a buffer circuit which provides the data complement input signal to the first driver and the data true input signal to the second driver;
a fourth test pad, wherein a signal on the fourth test pad is an input signal of the buffer circuit;
a pad connected to an output pin of the integrated circuit memory device;
a TTL (transistor-transistor logic) buffer connected to the pad, wherein a signal on the pad is an input signal of the TTL buffer;
a first inverter connected to the TTL buffer, which has an output signal of the TTL buffer as an input signal;
a passgate connected to the first inverter and controlled by the test mode signal
and a test mode complement signal, wherein the test mode signal and the test mode complement signal determine when an output signal of the first inverter will be inverted and presented as a first input signal to a first logic element also having the test mode signal as a second input signal and wherein the output signal of the first inverter passes through a latch comprised of a second inverter connected to a third inverter before being presented as the first input signal to the first logic element;
a second logic element having an output enable input signal, the test mode as an input signal, and an output signal;
a third logic element having the output signal of the second logic element as a first input signal, a write signal as a second input signal, and an output signal;
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a gate of the first transistor and a gate of the sixth transistor are controlled by an output signal of the first logic element, a first terminal of the first transistor is connected to the first supply voltage, and a second terminal of the first transistor is connected to a first terminal of the second transistor and a first terminal of the third transistor;
wherein a gate of the second transistor and a gate of the fourth transistor are controlled by the output signal of the TTL buffer;
wherein a gate of the third transistor and a gate of the fifth transistor are controlled by the output signal of the third logic element;
wherein a second terminal of the second transistor, a second terminal of the third transistor, a first terminal of the fourth transistor, a first terminal of the sixth transistor are connected to the data complement input signal;
wherein a second terminal of the fourth transistor is connected to a first terminal of the fifth transistor;
and wherein a second terminal of the fifth transistor and a second terminal of the sixth transistor are connected to a second supply voltage;
and
a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein a gate of the seventh transistor is connected to the output signal of the first logic element, the gate of the first transistor, the gate of the sixth transistor and a gate of the twelfth transistor;
wherein a first terminal of the seventh transistor is connected to the first supply voltage;
wherein a second terminal of the seventh transistor is connected to a first terminal of the eighth transistor and a first terminal of the ninth transistor;
wherein a gate of the eighth transistor and a gate of the tenth transistor are controlled by an inverse signal of the output signal of the TTL buffer;
wherein a gate of the ninth transistor and a gate of the eleventh transistor are controlled by the output signal of the third logic element;
wherein a second terminal of the eighth transistor, a second terminal of the ninth transistor, a first terminal of the tenth transistor, and a first terminal of the twelfth transistor are connected to the data true input signal;
wherein a second terminal of the tenth transistor is connected to a first terminal of the eleventh transistor;
and wherein a second terminal of the eleventh transistor and a second terminal of the twelfth transistor are connected to the second supply voltage.

29 more elements

Dependencies are inferred from the claim text.

Circuitry and methodology to test single bit failures of integrated circuit memory devices

Life of this patent

Circuitry and methodology to test single bit failures of integrated circuit memory devices

Life of this patent

Abstract

Claims40