Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability

A parallel binary adder comprising an array of complementary metal oxide semiconductor (CMOS) circuit blocks arranged in a plurality of columns of evaluation logic and a column of reset logic, a first column of said evaluation logic comprising a carry generator circuit (CGEN) and a plurality of propagate/generate/zero (PGZ) generator circuits (PGEN) circuits each receiving least significant bits (LSBs) and a carry input, intermediate columns of buffer and merge logic blocks connected to said CGEN and PGEN circuits, followed by a column of final sum (FSUM) circuits, and a final column of partial sum (PSUM) circuits, said PSUM circuits receiving said first and second binary inputs and providing partial sum signals to said FSUM circuits, said FSUM circuits outputting a binary result, said merge logic blocks calculating a carry out of a most significant bit (MSB), each of said CGEN, PGEN, merge and FSUM circuits comprising a self-resetting logic block including a logic tree connected to an output inverter, a half-latch connected to the output inverter and resetting devices connected to outputs of the logic tree and the output inverter and responsive to timed reset signals, said adder further comprising a reset timing chain connected to the row reset logic and generating said timed reset signals, the evaluation logic implementing an adder bubble pipelined circuit logic architecture in which a bubble pipeline segment consists of a column of self-resetting circuit blocks allowing a fast cycle time and minimum delay for each block by using fast forward amplification of a leading edge of pulsed input signals followed by quick self-resetting of all nodes back to a standby state.