Fast fourier transform dedicated processor

A Fast Fourier Transform dedicated processor (P), including a memory means (MM) to store an input data sequence (x(i)), a scrambling means (SM) to scramble said input data sequence (x(i)) thereby generating a plurality of scrambled data subsequences (a(i), b(i)), said scrambling means (SM) being coupled to an input of an arithmetic unit (AU), generating a Fast Fourier Transform output sequence (X(i)) from said scrambled data subsequences (a(i), b(i)), characterized in that to process a real said input data sequence (x(i)) said processor (P) additionally includes a data generation circuit (GC) which is connected between said scrambling means (SM) and said arithmetic unit (AU) and is adapted to derive from pairs of said scrambled data subsequences (a(i), b(i)) a complex data sequence (y(i)), and that said arithmetic unit (AU) includes an arithmetic means (AM), a data regeneration circuit (RC) and a combinatorial means (CM), said arithmetic means (AM) being adapted to recursively execute Decimate In Time Fast Fourier Transform steps on said complex data sequence (y(i)) thereby generating an intermediate Fast Fourier Transform series (Y(i)), said data regeneration circuit (RC) being adapted to generate from said intermediate Fast Fourier Transform series (Y(i)) individual Fast Fourier Transform series (A(i), B(i)) of said pair of scrambled data subsequences (a(i), b(i)), and said combinatorial means (CM) being adapted to execute a final Decimate In Time Fast Fourier Transform step on said individual Fast Fourier Transform series (A(i), B(i)) to thereby provide said Fast Fourier Transform output sequence (X(i)).