Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits

Abstract

An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fault simulation (TGFS) comparator is implemented in the PLD or FPGA consisting of a partitioned sub-circuit configuration, and a multiplicity of copies of the same configuration each with a single and different fault introduced in it. The method for test vector generation involves determining test vectors that flag each of the fault as determined by a comparison of the outputs of the good and single fault configurations. Further the method handles both combinational as well as sequential type circuits which require generating a multiplicity of test vectors for each fault. The successful test vectors are now propagated to the inputs and outputs of the electronic circuit, through driver and receiver sub-circuits, modeled via their corresponding TGFS comparators, by means of an input/output/function messaging buses. A method of fault simulation utilizing the TGFS comparators working under a fault specific approach determines the fault coverage of the test vectors.

Dependencies are inferred from the claim text.