System and method for generating mask layouts

An automatic mask layout generating system for automatically generating a mask layout for fabricating an integrated circuit therefrom, the automatic mask layout generating system comprising:

• an input device for receiving input data, including a timing specification and a transistor netlist corresponding to the integrated circuit;
• a processing unit including:
• associated memory and stored programs, including a plurality of mask layout tools, including a cell library generation tool for generating a cell library of cell layouts from a cell netlist, a place-and-route tool for using the cell library to generate mask layout data, and a clustering tool for clustering the cell netlist;
• and
• a processor operated by an automatic mask layout generation program for iteratively applying the plurality of mask layout tools to process the timing specification and the transistor netlist of the input data by transistor sizing using the transistor sizing tool to generate a revised netlist, to generate the cell library of cells from the revised netlist using the cell library generation tool, to perform placing and routing of the cell library using the place-and-route tool, and to revise the revised netlist to generate a final netlist and the mask layout data corresponding to a final mask layout, wherein the clustering tool clusters the cell netlist generated by the transistor sizing tool into a plurality of supercells for use by the cell library generation tool to generate the cell library;
• and
• an output device for outputting the mask layout data to generate the final mask layout.

A method for generating a mask layout of an integrated circuit specified by a netlist and a timing specification, the method comprising the steps of:

• a) automatically sizing the transistors specified in the netlist to revise the netlist;
• b) clustering the sized transistors into supercells;
• c) generating a cell library of cells from the revised netlist, the supercells, and the timing specification;
• and
• d) placing and routing the cells to generate the mask layout of the integrated circuit.

A method for generating a mask layout of an integrated circuit specified by a netlist and a timing specification, the method comprising the steps of:

• a) automatically sizing the transistors specified in the netlist to revise the netlist;
• b) generating a cell library of cells from the revised netlist and the timing specification;
• c) placing and routing the cells to generate the mask layout of the integrated circuit;
• d) extracting performance characteristics from the mask layout;
• e) verifying the mask layout;
• and
• f) repeating steps (a)-(e) to revise the netlist until the extracted performance characteristics of the mask layout generated from the revised netlist attains a predetermined criteria.

A method for generating a mask layout of an integrated circuit specified by a netlist and a timing specification, the method comprising the steps of:

• a) automatically sizing the transistors specified in the netlist to revise the netlist;
• b) generating a cell library of cells from the revised netlist and the timing specification, including the steps of;
• b1) synthesizing a virtual grid layout for each cell from the netlist;
• b2) compacting each cell using the virtual grid layout to generate the cell library of cells;
• b3) determining whether each of the compacted cells has an associated cell height within a predetermined cell height specification;
• b4) reducing cell heights of cells that exceed the predetermined cell height specification by folding transistors with those cells;
• and
• b5) repeating steps (b1)-(b4) until each of the compacted cells has an associated cell height within the predetermined cell height specification;
• and
• c) placing and routing the cells to generate the mask layout of the integrated circuit.

A mask layout of an integrated circuit specified by a netlist and a timing specification, the mask layout generated by a method comprising the steps of:

• a) automatically sizing the transistors specified in the netlist to revise the netlist;
• b) clustering the sized transistors into supercells;
• c) generating a cell library of cells from the supercells, the revised netlist and the timing specification;
• and
• d) placing and routing the cells to generate the mask layout of the integrated circuit.

An integrated circuit specified by a netlist and a timing specification, the integrated circuit fabricated using a mask layout generated by a method comprising the steps of:

• a) automatically sizing the transistors specified in the netlist to revise the netlist;
• b) clustering the sized transistors into supercells;
• c) generating a cell library of cells from the supercells, the revised netlist and the timing specification;
• and
• d) placing and routing the cells to generate the mask layout of the integrated circuit.

A mask layout of an integrated circuit specified by a transistor netlist and a timing specification, the mask layout generated by a method comprising the steps of:

• a) automatically sizing the transistors specified in the transistor netlist to revise the transistor netlist to generate a cell netlist;
• b) clustering the cell netlist generated by the transistor sizing tool into a plurality of supercells;
• c) generating a cell library of cells from the cell netlist and the timing specification;
• and
• d) placing and routing the cells to generate the mask layout of the integrated circuit.

An integrated circuit specified by a transistor netlist and a timing specification, the integrated circuit fabricated using a mask layout generated by a method comprising the steps of:

• a) automatically sizing the transistors specified in the transistor netlist to revise the transistor netlist to generate a cell netlist;
• b) clustering the cell netlist generated by the transistor sizing tool into a plurality of supercells;
• c) generating a cell library of cells from the cell netlist and the timing specification;
• and
• d) placing and routing the cells to generate the mask layout of the integrated circuit.