Back to results
US 5,633,805 AGranted
Logic synthesis having two-dimensional sizing progression for selecting gates from cell libraries
AssigneeIntel Corporation
InventorCarl J. Simonsen
Life of this patent
Estimating the term…
Abstract
A logic synthesis method uses a two-dimensional sizing progression for selecting gates from a cell library in designing an integrated circuit. The drive load and desired performance for each logic gate in a functional configuration for the integrated circuit may be determined. The device configuration or gate to implement the logic gate may be selected from a cell library. The selected gate has a drive load range encompassing the determined drive load and achieves a desired performance target for the logic gate. A two-dimensional sizing progression may be used to help minimize layout area, power consumption, and performance loss in implementing BiNMOS gates.
Claims30
A logic synthesis method having two-dimensional sizing progression for selecting a logic gate to be implemented within a circuit, comprising the steps of:
- (a) determining a drive load and a desired performance for the logic gate;
- (b) determining a group of gates restricted to a drive load range encompassing the determined drive load from a cell library by utilizing a look-up table that contains at least a minimum drive load and a maximum drive load corresponding to each gate of said group of gates;
- and
- (c) selecting one gate from the group of gates to be used as the logic gate.
1 more element
A logic synthesis method having two-dimensional sizing progression for selecting a logic gate to be implemented within a circuit, comprising the steps of:
- (a) determining a drive load and a desired performance for the logic gate;
- (b) determining a group of gates restricted to a drive load range encompassing the determined drive load from a cell library, said drive load range being defined by a minimum drive load and a maximum drive load;
- and
- (c) selecting one gate from the group of gates to be used as the logic gate, wherein said selecting step includes
- (i) selecting one of the gates from the group of gates that is a smallest gate in physical size in the group of gates, and
- (ii) replacing the one gate selected in the selecting step (c)(i) with another gate from the group of gates based on the desired performance for the logic gate, the another gate being larger in physical size than the one gate selected in step (c)(i).
3 more elements
A logic synthesis method having two-dimensional sizing progression for selecting a logic gate to be implemented within a circuit, comprising the steps of:
- (a) determining a drive load and a desired performance for the logic gate to be implemented;
- (b) determining a group of gates restricted to a drive load range encompassing the determined drive load from a cell library that includes a plurality of sets of gates, each gate in one set of gates of the plurality of sets of gates is included in the group of gates and has a drive load range that encompasses the drive load and is approximately the same as the drive load range for any other gate in the one set of gates;
- and
- (c) selecting one gate from the group of gates to be used as the logic gate based on the desired performance for the logic gate.
1 more element
A system to design a circuit comprising:
- (a) memory which contains a cell library having a plurality of gates and a lookup table that identifies the plurality, of gates in the cell library, the look-up table further contains a minimum drive load and a maximum drive load for each of the plurality of gates;
- (b) first circuitry that determines a drive load and a desired performance for a logic gate to be implemented within the circuit;
- (c) second circuitry that determines from the look-up table of the cell library a group of gates restricted to a drive load range encompassing the drive load;
- and
- (d) third circuitry that selects one gate from the group of gates to be used as the logic gate.
2 more elements
A system to design a circuit comprising:
- (a) memory which contains a cell library having a plurality of gates;
- (b) first circuitry that determines a drive load and a desired performance for a logic gate to be implemented within the circuit;
- (c) second circuitry that determines from the cell library a group of gates restricted to a drive load range encompassing the drive load, said drive load range being defined by a minimum drive load and a maximum drive load;
- and
- (d) third circuitry that selects one gate from the group of gates to be used as the logic gate.
2 more elements
A system to design a circuit comprising:
- (a) memory which contains a cell library having a plurality of sets of gates, each gate in one set of gates of the plurality of sets of gates having a drive load range that encompasses the drive load and is approximately the same as the drive load range for any other gate in the one set of gates;
- (b) first circuitry that determines a drive load and a desired performance for a logic gate to be implemented within the circuit;
- (c) second circuitry that determines from the cell library a group of gates restricted to a drive load range encompassing the drive load, said drive load range being defined by a minimum drive load and a maximum drive load;
- and
- (d) third circuitry that selects one gate from the group of gates to be used as the logic gate based on the desired performance for the logic gate.
2 more elements
A system to design a circuit comprising:
- (a) first means for storing a cell library having a plurality of gates and a look-up table that identifies the plurality of gates in the cell library and that contains a minimum drive load and a maximum drive load for each of the plurality of gates;
- (b) second means for determining a drive load and a desired performance for a logic gate to be implemented within the circuit;
- (c) third means for determining from the look-up table of the cell library a group of gates restricted to a drive load range encompassing the drive load;
- and
- (d) fourth means for selecting one gate from the group of gates to used as the logic gate based on the desired performance for the logic gate.
2 more elements
A system to design a circuit comprising:
- system
- (a) first means for storing a cell library having a plurality of gates;
- (b) second means for determining a drive load and a desired performance for a logic gate to be implemented within the circuit;
- (c) third means for determining from the cell library a group of gates restricted to a drive load range encompassing the drive load, said drive load range being defined by a minimum drive load and a maximum drive load;
- and
- (d) fourth means for selecting one gate from the group of gates to be used as the logic gate based on the desired performance for the logic gate.
3 more elements
A system to design a circuit comprising:
- (a) first means for storing a cell library having a plurality of sets of gates, each gate in one set of gates of the plurality of sets of gates having a drive load range that encompasses the drive load and is approximately the same as the drive load range for any other gate in the one set of gates;
- and
- (b) second means for determining a drive load and a desired performance for a logic gate to be implemented;
- (c) third means for determining from the cell library a group of gates restricted to a drive load range encompassing the drive load, said drive load range being defined by a minimum drive load and a maximum drive load;
- and
- (d) fourth means for selecting one gate from the group of gates to be used as the logic gate.
3 more elements
A logic synthesis method having two-dimensional sizing progression for selecting a logic gate to be implemented within a circuit, comprising the steps of:
- (a) determining a switching time delay and a desired drive load for the logic gate;
- (b) determining a group of gates, restricted to a switching time delay range encompassing the determined switching time delay, from a cell library by utilizing a look-up table that contains at least a minimum switching time delay and a maximum switching time delay corresponding to each gate of said group of gates;
- and
- (c) selecting one gate from the group of gates to be used as the logic gate based on satisfying the desired drive load.
1 more element
Dependencies are inferred from the claim text.