Process for the processing of specification data of logic functions of an application-specific integrated circuit

Process for the processing of logic function specification data of an application-specific integrated circuit (ASIC), which has gates, electrical connections between the gates and functional assemblies, the process comprising:

• a) acquiring logic function specification data of the circuit, said data respectively relating to combinational or sequential gates, functional assemblies, connectors and links between connectors, the link data being associated with the connector data, and the connector data comprising:
• 1) data of input and output connectors of gates, with which are respectively associated the gate data,
• 2) data of pairs of internal/external, input and output connectors of functional assemblies, with which are respectively associated the functional assembly data and
• 3) data of input and output connectors of the circuit,
• b) associating with each connector data item a Boolean attribute known as an "extraction" attribute able to respectively assume a first or so-called "true" value (1) and a second or so-called "false" value (0), the extraction attribute being determined in accordance with a representation rule or being chosen by a circuit designer, an identical attribute being respectively associated with the data of the connectors of the same gate and with the data of connectors of a same pair of connectors,
• c) associating a so-called "node" identifier, which is different for each connector data item having a "true" Boolean extraction attribute, and associating an identical identifier with each connector data item either of a same gate, or of a same pair of connectors, said connector data item having a "false" Boolean attribute,
• d) associating a so-called "arc" link identifier with the data of connectors for which there is a link data item and which have different node identifiers,
• e) forming maximum assemblies of connectors, which have different node identifiers and which have at least one arc identifier in common with one of the connectors of a maximum assembly and associating a so-called "block" identifier with all the connectors of the same maximum assembly,
• f) associating a so-called "input half-edge" identifier with all the data of output connectors having a "true" extraction attribute and associating a so-called "output half-edge" identifier with all the data of input connectors having a "true" extraction attribute,
• g) associating with each half-edge identifier a Boolean attribute known as a link attribute and able to assume a first or so-called "true" value and a second or so-called "false" value, the link attribute being determined in accordance with a representation rule or being chosen by a circuit designer,
• h) seeking couples of connectors of the same pair of connectors, or a same gate, such that the connectors of each couple of connectors respectively have a different block identifier, and a respectively input and output half-edge identifier having a "false" link attribute and association of a block edge identifier, respectively with each block having a connector of the couple of connectors.