Power converter control system

A control system for a pulse-width modulation controlled power converter, said power converter being composed of self-turn-off devices, said control system comprising:

• voltage command value generating means for generating a voltage command value for an output voltage of said power converter;
• carrier wave generator means for generating a carrier wave with a frequency;
• correction means for correcting said voltage command value to generate as a corrected voltage command value e.sub.2 ;
• and
• gate pulse signal generating means for receiving a first signal and a second signal as two input signals and for comparing said first signal with said second signal to generate gate pulse signals to self-turn-off devices for controlling said output voltage of said power converter based on a comparison result;
• said voltage command value being taken as e (-1.ltoreq.e.ltoreq.+1), and a level setting value being taken as E.sub.a (0<Ea<1);
• said gate pulse signal generating means receiving said voltage command value as said first signal and said carrier wave as said second signal when -E.sub.a .ltoreq.e.ltoreq.+E.sub.a ;
• and
• said gate pulse signal generating means receiving said corrected voltage command value as said first signal and said carrier wave as said second signal when e<-E.sub.a or +E.sub.a <e, wherein
• said correction means includes:
• an adder for adding said voltage command value (e) and a sample-held error signal (.DELTA.e);
• a first sample hold circuit for sample-holding an output signal e.sub.1 (e+.DELTA.e) of said adder every specified cycle;
• a signal correction circuit connected to receive said output signal (e.sub.1 =e+.DELTA.e) of said first sample hold circuit for generating said corrected voltage command value (e.sub.2);
• a subtractor for generating said error signal (.DELTA.e) by subtracting said corrected voltage command value (e.sub.2) from said output signal (e.sub.1) of said first sample hold circuit;
• and
• a second sample hold circuit for sample-holding said error signal (.DELTA.e) every said specified cycle at a timing which is delayed from the sample hold timing of said first sample hold circuit;
• and
• wherein said corrected voltage command value (e.sub.2) is determined by comparing said output signal (e.sub.1) with said level setting value (E.sub.a) and a level setting value E.sub.b, .paren open-st.0<E.sub.a <E.sub.b .paren close-st. as follows:
• ______________________________________ when -E.sub.b >
• e.sub.1' e.sub.2 = -1;
• when -E.sub.b <
• e.sub.1 <
• -E.sub.a' e.sub.2 = -E.sub.a ;
• when -E.sub.a <
• e.sub.1 <
• +E.sub.a' e.sub.2 = e.sub.1 ;
• when +E.sub.a <
• e.sub.1 <
• +E.sub.b' e.sub.2 = +E.sub.a ;
• and when +E.sub.b <
• e.sub.1', e.sub.2 = +1. ______________________________________

A control system for a pulse-width modulation controlled power converter, said power converter being composed of self-turn-off devices, said control system comprising:

• voltage command value generating means for generating a voltage command value for an output voltage of said power converter;
• carrier wave generator means for generating a carrier wave with a frequency;
• gate pulse signal generating means for receiving said voltage command value and said carrier wave as two input signals and for comparing said voltage command value and said carrier wave to generate gate pulse signals based on a comparison result;
• and
• correction means connected to receive said voltage command value and said gate pulse signals for generating corrected gate pulse signals to said self-turn-off devices for controlling said output voltage of said power converter;
• said voltage command value being taken as e (-1.ltoreq.e.ltoreq.+1), and a level setting value being taken as E.sub.a (0<E.sub.a <1);
• said correction means generating said gate pulse signals as said corrected gate pulse signals as they stand, when -E.sub.a .ltoreq.e.ltoreq.+E.sub.a ;
• and
• said correction means correcting a pulse-width (ti) of said gate pulse signals when e<-E.sub.a or +E.sub.a <e and generating gate pulse signals with a corrected pulse-width (ti') as said corrected gate pulse signals only when said corrected pulse-width (ti') is equal to or larger than a set time (ts).