Controlling apparatus for display of an on-screen menu in a display device

An apparatus for controlling an on-screen menu, comprising:

• a first data bus having a plurality of data lines including a least significant bit line, the first data bus being for transmitting display information to a character generator, the display information including alphanumeric data and attribute data relating to the on-screen menu;
• a display buffer coupled to the first data bus for storing the display information, generating the alphanumeric data when a select signal is in a prescribed logic state, and generating the attribute data when the select signal is the complement of the prescribed logic state;
• a read-only memory means coupled to the first data bus for generating a character signal in response to the alphanumeric data;
• a second data bus coupled to the read-only memory for transmitting the character signal;
• a shift register coupled to the second data bus for receiving the character signal at a first time point in response to the complement of a control signal;
• and
• a latch circuit coupled to the first data bus for generating the select signal in response to the control signal, the select signal causing the display buffer to transmit the attribute data;
• wherein all of the data lines of the first data bus are operable to transmit the alphanumeric data when the select signal is in the prescribed logic state, and all of the data lines of the first data bus are operable to transmit the attribute data when the select signal is the complement of the prescribed logic state.

An apparatus for controlling an on-screen menu, comprising:

• a first data bus having a plurality of data lines including a least significant bit line, the first data bus being for transmitting display information, the display information including alphanumeric data and attribute data relating to the on-screen menu;
• a display buffer coupled to the first data bus for storing the display information, generating the alphanumeric data when a select signal is in a prescribed logic state, and generating the attribute data when the select signal is the complement of the prescribed logic state;
• a read-only memory means coupled to the first data bus for generating a character signal in response to the alphanumeric data;
• a second data bus coupled to the read-only memory for transmitting the character signal;
• a shift register coupled to the second data bus for receiving the character signal at a first time point in response to the complement of a control signal;
• a latch circuit coupled to the least significant bit line of the first data bus for generating the select signal in response to the control signal, the select signal causing the display buffer to transmit the attribute dam, the latch circuit latching the attribute data at a second time point, the latch circuit comprising:
• a counter having three output terminals;
• an AND gate having three input terminals coupled to the three counter output terminals, the AND gate generating the control signal at an AND gate output terminal;
• a first NOR gate having two input terminals connected to two of the counter output terminals, and a first NOR gate output terminal;
• a second NOR gate having two inputs terminals connected to the AND gate output terminal and the first NOR gate output terminal, the second NOR gate generating a second output signal at a second NOR gate output terminal;
• a first flip-flop having a first flip-flop data input terminal coupled to the first data bus, a first flip-flop clock input terminal coupled to the second NOR gate output terminal, and a first flip-flop output terminal, the first flip-flop being for latching the attribute data from the first data bus in response to the second output signal;
• a second flip-flop having a second flip-flop data input terminal coupled to the first flip-flop output terminal, a second flip-flop clock input terminal coupled to the AND gate output terminal, and a second flip-flop output terminal, the second flip-flop being for transmitting the attribute data in response to the application of the control signal;
• and
• gate circuitry coupled to the second NOR gate output terminal for generating the select signal in response to the second output signal, an on-screen menu display control signal and a display buffer access control signal.