Data rate conversion circuit
AssigneeAG Communication Systems Corporation
InventorChristopher A. Pawlowski
Life of this patent
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Abstract
A data conversion circuit that acts as an interface between components or systems having different data input/output rate requirements. A circuit reads data transmitted at one bit rate and transmits data consisting of the input data along with overhead data interleaved with the input data in a fixed pattern at a faster bit rate. Also disclosed is a circuit that operates to read data at a faster bit rate and transmit data consisting of the input data stripped of interleaved overhead data at a slower bit rate. Data is written into and read from a register array that allows data to be concurrently and independently written and read. A suitable delay is introduced on the output side in order to avoid read/write collisions in the register array and achieve a minimum transmission delay.
Claims16
A data rate conversion circuit for use in a data transmission system having first and second data systems, said first data system being operated to transmit a synchronization signal, a first clock signal, a second clock signal and first data having a first data pattern comprising a serial bit stream of consecutive data frames forming a span, each of said data frames having a predetermined number of channel words, each of said words having a predetermined number of bits, said first data further including a first data rate corresponding to said first clock signal, said second data system being operated to receive said second clock signal and data having a second data pattern and a second data rate corresponding to said second clock signal, said data rate conversion circuit comprising:
- storage means having an input storage location;
- said storage means further comprising a stuffed storage location containing a stuffed word of predetermined pattern;
- write control means connected between said first data system and said storage means, operated to receive said first data and to consecutively write each channel word into said input storage location at a rate related to said first data rate;
- and
- read control means connected between said storage means and said second data system, and operated to read said channel words from said input storage location and said stuffed word from said stuffed storage location at a rate related to said second data rate, said channel and stuffed words being read to form said second data pattern by periodically reading said stuffed word after a predetermined number of said channel words.
A data rate conversion circuit for use in a data transmission system having first and second data systems, said first data system being operated to transmit a synchronization signal, a first clock signal, a second clock signal and first data having a first data pattern comprising a serial bit stream of consecutive data frames forming a span, each of said data frames having a predetermined number of channel words and stuffed words, each of said channel and stuffed words having a predetermined number of bits, said channel and stuffed words interleaved to form a predetermined pattern, said first data further including a first data rate corresponding to said first clock signal, said second data system being operated to receive said second clock signal and data having a second data pattern and a second data rate corresponding to said second clock signal, said data rate conversion circuit comprising:
- storage means having an input storage location;
- write control means connected between said first data system and said storage means, operated to receive said first data and to consecutively write each of said channel words into said input storage location at a rate related to said first data rate;
- and
- read control means connected between said storage means and said second data system, operated to read said channel words from said input storage location at a rate related to said second data rate, convert said first data to said second data, and transmit said second data to said second data system.
Dependencies are inferred from the claim text.